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| Datasheet File OCR Text: |
| january 2011 doc id 12370 rev 8 1/324 1 st72561xx-auto 8-bit mcu for automotive with flash or rom, 10-bit adc, 5 timers, spi, linsci?, active can features memories ? 16 k to 60 k high density flash (hdflash) or rom with read-out protection capability. in-application programming and in-circuit programming for hdflash devices ? 1 to 2 k ram ? hdflash endurance: 100 cycles, data retention 20 years at 55 c clock, reset and supply management ?low power crystal/ ceramic resonator oscillators and bypass for external clock ? pll for 2 x frequency multiplication ? 5 power saving modes: halt, auto wake up from halt, active halt, wait and slow interrupt management ? nested interrupt controller ? 14 interrupt vectors plus trap and reset ? tli top level interrupt (on 64-pin devices) ? up to 21 ext. interrupt lines (on 4 vectors) up to 48 i/o ports ? up to 48 multifunctional bidirectional i/os ? up to 36 alternate i/o functions ? up to 6 high sink outputs 5 timers ? 16-bit timer with 2 input captures, 2 output compares, external clock input, pwm and pulse generator modes ? 8-bit timer with 1 or 2 input captures, 1 or 2 output compares, pwm and pulse generator modes ? 8-bit pwm auto-reload timer with 1 or 2 input captures, 2 or 4 independent pwm output channels, output compare and time base interrupt, external clock with event detector ? main clock controller with real-time base and clock output ? window watchdog timer up to 4 communications interfaces ? spi synchronous serial interface ? master/ slave linsci? asynchronous serial interface ? master only linsci? asynchronous serial interface ? can 2.0b active analog peripheral (low current coupling) ? 10-bit a/d converter with up to 16 inputs ? up to 9 robust ports (low current coupling) instruction set ? 8-bit data manipulation ? 63 basic instructions, 17 main addressing modes ? 8 x 8 unsigned multiply instruction development tools ? full hardware/ software development package table 1. device summary reference part number st72561xx- auto st72561k4-auto, st72561k6-auto, st72561k7-auto, st72561k9-auto, st72561j4-auto, st72561j6-auto, st72561j7-auto, st72561j9-auto, st72561r4-auto, st72561r6-auto, st72561r7-auto, st72561r9-auto, st72561ar4-auto, st72561ar6-auto, st72561ar7-auto, ST72561AR9-AUTO lqfp32 7x7mm lqfp44 10x10mm lqfp64 14x14mm lqfp64 10x10mm www.st.com
contents st72561-auto 2/324 doc id 12370 rev 8 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.1 read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.2 index registers (x and y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.3 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.4 condition code register (cc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.5 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 st72561-auto contents doc id 12370 rev 8 3/324 5.5.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5.3 external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5.4 internal low voltage detector (lvd) reset . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5.5 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.6 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.6.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.6.2 auxiliary voltage detector (avd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.6.3 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.6.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.6.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.5.1 cpu cc register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.5.2 interrupt software priority registers (isprx) . . . . . . . . . . . . . . . . . . . . . 55 6.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.5 active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.6 auto wake-up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.6.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 contents st72561-auto 4/324 doc id 12370 rev 8 8.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.4 i/o port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.4.1 standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.4.2 interrupt ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.4.3 pull-up input port (cantx requirement) . . . . . . . . . . . . . . . . . . . . . . . . 79 8.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.4 using halt mode with the wdg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.5 how to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.7 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.8 using halt mode with the wdg (wdghalt option) . . . . . . . . . . . . . . . . 87 9.9 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.10.1 control register (wdgcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.10.2 window register (wdgwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10 main clock controller with real time clock mcc/rtc . . . . . . . . . . . . . . 89 10.1 programmable cpu clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.2 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.3 real time clock timer (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.6.1 mcc control/status register (mccsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11 pwm auto-reload timer (art) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 st72561-auto contents doc id 12370 rev 8 5/324 11.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.2 counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.3 counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.4 output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.5 independent pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.2.6 output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . 96 11.2.7 external clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 96 11.2.8 input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.2.9 external interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.3 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.3.4 procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.3.5 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3.6 procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3.7 forced compare outp ut capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.3.8 one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.3.9 pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.7.1 control register 1 (cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.7.2 control register 2 (cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.7.3 control/status register (csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.7.4 input capture 1 high register (ic1hr) . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.7.5 input capture 1 low register (ic1lr) . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.7.6 output compare 1 high register (oc1hr) . . . . . . . . . . . . . . . . . . . . . . 122 12.7.7 output compare 1 low register (oc1lr) . . . . . . . . . . . . . . . . . . . . . . . 122 contents st72561-auto 6/324 doc id 12370 rev 8 12.7.8 output compare 2 high register (oc2hr) . . . . . . . . . . . . . . . . . . . . . . 122 12.7.9 output compare 2 low register (oc2lr) . . . . . . . . . . . . . . . . . . . . . . . 123 12.7.10 counter high register (chr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.7.11 counter low register (clr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.7.12 alternate counter high register (achr) . . . . . . . . . . . . . . . . . . . . . . . . 123 12.7.13 alternate counter low register (aclr) . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.7.14 input capture 2 high register (ic2hr) . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.7.15 input capture 2 low register (ic2lr) . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13 8-bit timer (tim8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.3.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.3.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.3.4 forced compare outp ut capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.3.5 one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13.3.6 pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.7.1 control register 1 (cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.7.2 control register 2 (cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.7.3 control/status register (csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.7.4 input capture 1 register (ic1r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.7.5 output compare 1 register (oc1r) . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.7.6 output compare 2 register (oc2r) . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.7.7 counter register (ctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.7.8 alternate counter register (actr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.7.9 input capture 2 register (ic2r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.8 8-bit timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14 serial peripheral interface (spi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 st72561-auto contents doc id 12370 rev 8 7/324 14.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.3.2 slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.3.3 master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.3.4 master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.3.5 slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.3.6 slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.4 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.5 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.5.1 master mode fault (modf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.5.2 overrun condition (ovr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.5.3 write collision error (wcol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.8.1 control register (spicr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.8.2 control/status register (spicsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.8.3 data i/o register (spidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15 linsci serial communicatio n interface (lin master/s lave) . . . . . . . . 158 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.2 sci features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.3 lin features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.5 sci mode - functional descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 15.5.1 conventional baud rate generator mode . . . . . . . . . . . . . . . . . . . . . . . 160 15.5.2 extended prescaler mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.5.3 serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.5.4 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.5.5 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.5.6 extended baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.5.7 receiver muting and wake-up feature . . . . . . . . . . . . . . . . . . . . . . . . . 166 15.5.8 parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 contents st72561-auto 8/324 doc id 12370 rev 8 15.8 sci mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.8.1 status register (scisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.8.2 control register 1 (scicr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.8.3 control register 2 (scicr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.8.4 data register (scidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.8.5 baud rate register (scibrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.8.6 extended receive prescaler division register (scierpr) . . . . . . . . . . 174 15.8.7 extended transmit prescaler division register (scietpr) . . . . . . . . . . 175 15.9 lin mode - functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.9.1 entering lin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.9.2 lin transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.9.3 lin reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.9.4 lin error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.9.5 lin baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.9.6 lin slave baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.9.7 linsci clock tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.9.8 clock deviation causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.9.9 error due to lin synch measurement . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.9.10 error due to baud rate quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.9.11 impact of clock deviation on maximum baud rate . . . . . . . . . . . . . . . . 185 15.10 lin mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.10.1 status register (scisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.10.2 control register 1 (scicr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.10.3 control register 2 (scicr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.10.4 control register 3 (scicr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.10.5 lin divider registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.10.6 lin prescaler register (lpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.10.7 lin prescaler fraction register (lpfr) . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.10.8 lin header length register (lhlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16 linsci serial communicatio n interface (lin master only) . . . . . . . . 195 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.4.1 serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 st72561-auto contents doc id 12370 rev 8 9/324 16.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 16.4.4 conventional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 16.4.5 extended baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.4.6 receiver muting and wake-up feature . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.4.7 parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 16.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.7 sci synchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.8.1 status register (scisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.8.2 control register 1 (scicr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.8.3 control register 2 (scicr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.8.4 control register 3 (scicr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.8.5 data register (scidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.8.6 baud rate register (scibrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.8.7 extended receive prescaler division register (scierpr) . . . . . . . . . . 214 16.8.8 extended transmit prescaler division register (scietpr) . . . . . . . . . . 214 17 becan controller (becan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 17.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 17.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 17.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 17.4.1 transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 17.4.2 reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 17.4.3 identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 17.4.4 message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17.4.5 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 17.4.6 bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 17.6 register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 17.7 becan cell limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.7.1 fifo corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17.8.1 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 contents st72561-auto 10/324 doc id 12370 rev 8 17.8.2 can transmit status register (ctsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.8.3 mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 17.8.4 can filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 18.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 18.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 18.3.1 digital a/d conversion result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 18.3.2 a/d conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 18.3.3 changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.3.4 adcdr consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.6.1 control/status register (adccsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.6.2 data register (adcdrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18.6.3 data register (adcdrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 19 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 19.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 19.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 19.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 19.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 19.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 19.2.1 using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 20 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 20.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 20.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 20.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 20.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 st72561-auto contents doc id 12370 rev 8 11/324 20.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 20.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 20.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 20.2.1 voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 20.2.2 current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 20.2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 20.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 20.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 20.3.2 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . 275 20.3.3 auxiliary voltage detector (avd) thresholds . . . . . . . . . . . . . . . . . . . . . 276 20.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 20.4.1 supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 20.4.2 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 20.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 20.5.1 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 280 20.5.2 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 20.6 auto wakeup from halt oscillator (awu) . . . . . . . . . . . . . . . . . . . . . . . . . 282 20.7 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 20.7.1 ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 20.7.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 20.8 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 20.8.1 functional ems (ele ctromagnetic susc eptibility) . . . . . . . . . . . . . . . . . 283 20.8.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 20.8.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 284 20.9 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 20.9.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 20.9.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 20.10 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 20.10.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 20.10.2 iccsel/ vpp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 20.11 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 20.12 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 295 20.12.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 20.12.2 can - controller area network interface . . . . . . . . . . . . . . . . . . . . . . . . 297 20.13 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 contents st72561-auto 12/324 doc id 12370 rev 8 21 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 21.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 21.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 21.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 21.4 packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 22 device configuration and ordering informati on . . . . . . . . . . . . . . . . . 306 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 22.2 flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 22.2.1 flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 22.2.2 flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 22.3 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 23 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 24 important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 24.1 all devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 24.1.1 reset pin protection with lvd enabled . . . . . . . . . . . . . . . . . . . . . . . 315 24.1.2 clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 315 24.1.3 external interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 24.1.4 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 24.1.5 header time-out does not prevent wake-up from mute mode . . . . . . . 318 24.1.6 can fifo corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 24.2 flash/fastrom devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 24.2.1 linsci wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 24.2.2 16-bit and 8-bit timer pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 24.3 rom devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 24.3.1 16-bit timer pwm mode buffering feature change . . . . . . . . . . . . . . . . 321 25 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 st72561-auto list of tables doc id 12370 rev 8 13/324 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 3. device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 4. hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5. sectors available in flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6. flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7. interrupt software priority selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 8. st7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 9. effect of low power modes on si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 10. interrupt control/wake -up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 11. reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 12. interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 13. interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 14. interrupt priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 15. dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 16. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 17. interrupt sensitivity - ei3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 18. interrupt sensitivity - ei2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 19. interrupt sensitivity - ei1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 20. interrupt sensitivity - ei0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 21. nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 22. mcc/rtc low power mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 23. awupr prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 24. awu register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 table 25. dr register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 26. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 27. i/o port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 28. configuration of pb7:6, pc0, pc3, pc7:5, pd3:2, pd5, pe7:0, pf7:0 . . . . . . . . . . . . . . . 77 table 29. configuration of pa0, 2, 4, 6; pb0, 2,4; pc1; pd0,6 (with pull-up) . . . . . . . . . . . . . . . . . . 78 table 30. configuration of pa1, 3, 5, 7; pb1,3,5; pc2; pd1, 4, 7 (without pull-up) . . . . . . . . . . . . . . 78 table 31. configuration of pc4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 32. port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 33. effect of low power modes on i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 table 34. i/o port interrupt cont rol/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 table 35. i/o port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 36. effect of low power modes on wdg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 37. watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 38. effect of low power modes on mcc/rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 39. mcc/rtc interrupt control wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 40. cpu clock frequency in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 41. time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 42. main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 43. counter clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 44. pwm frequency vs resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 45. pwmx output level and polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 46. pwm auto-reload timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 47. effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 48. timer interr upt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 list of tables st72561-auto 14/324 doc id 12370 rev 8 table 49. timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 50. clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 51. 16-bit timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 52. effect of low power modes on tim8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 53. tim8 interrupt control and wake-u p capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 54. timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 55. clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 56. effect of low power modes on spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 53 table 57. spi interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 58. spi master mode sck frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 59. spi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 60. character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 61. effect of low power modes on sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 68 table 62. sci interrupt c ontrol and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 63. pr prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 64. transmitter rate divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 65. receiver rate divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 66. lin mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 67. ldiv mantissa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 68. ldiv fraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 69. lhl mantissa coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 70. lhl fraction coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 71. linsci1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 72. frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 73. effect of low power modes on sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 05 table 74. sci interrupt c ontrol and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 75. lin sync break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 76. sci clock on sclk pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 77. pr prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 78. transmitter rate divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 79. receiver rate divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 80. baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 81. linsci2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 82. transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 83. receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 84. while loop timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 table 85. lec error types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 86. filter page selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 table 87. becan control and status page - register map and reset values . . . . . . . . . . . . . . . . . . . 257 table 88. becan mailbox pages - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 257 table 89. becan filter configuration page - register map and reset values . . . . . . . . . . . . . . . . . . . 258 table 90. effect of low power modes on adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 table 91. a/d clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 92. adc channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 93. adc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 table 94. addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 table 95. cpu addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 table 96. instructions supporting direct, indexed, indi rect and indirect indexed addressing (part 1) 267 table 97. instructions supporting direct, indexed, indi rect and indirect indexed addressing (part 2) 267 table 98. instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 table 99. supply current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 table 100. clock source current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 78 st72561-auto list of tables doc id 12370 rev 8 15/324 table 101. peripheral consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 table 102. general timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 103. external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 104. oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 table 105. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 table 106. awu oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 table 107. ram supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 table 108. dual voltage hdflash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 table 109. ems test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 table 110. emi emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 table 111. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 table 112. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 table 113. i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 table 114. output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 115. reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 table 116. iccsel/v pp pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 table 117. 8-bit pwm-art auto reload timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 118. 8-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 119. 16-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 120. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 table 121. can characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 122. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 123. adc accuracy with f cpu = 8 mhz, f adc = 4 mhz r ain < 10kw, v dd = 5v. . . . . . . . . . . . 300 table 124. package selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 table 125. alternate function remapping 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 126. alternate function remapping 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 127. osctype selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 128. oscrange selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 129. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 list of figures st72561-auto 16/324 doc id 12370 rev 8 list of figures figure 1. device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 2. lqfp 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 3. lqfp 44-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. lqfp 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 6. memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 7. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 8. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 9. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 10. pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 11. clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12. reset sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 13. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 14. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15. low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 16. using the avd to monitor vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17. interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 18. priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 19. concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 20. nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 21. external interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 22. power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 23. slow mode clock transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 24. wait mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 25. halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 26. halt mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 27. active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 28. active halt mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 29. awufh mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 30. awuf halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 31. awufh mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 32. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 33. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 34. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 35. approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 36. exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 37. window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 38. main clock controller (mcc/rtc) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 39. pwm auto-reload timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 40. output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 41. pwm auto-reload timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 42. pwm signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 43. external event detector example (3 counts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 44. input capture timing diagram, fcounter = fcpu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 45. input capture timing diagram, fcounter = fcpu / 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 46. art external interrupt in halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 47. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 48. 16-bit read sequence: (from counter or alternate counter register) . . . . . . . . . . . . . . . . . 106 st72561-auto list of figures doc id 12370 rev 8 17/324 figure 49. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 50. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 51. counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 52. input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 53. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 54. output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 55. output compare timing diagram, ftimer = fcpu/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 56. output compare timing diagram, ftimer = fcpu/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 57. one pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 15 figure 58. pulse width modulation mode timing example with 2 output compare functions . . . . . . . 115 figure 59. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 60. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 61. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 62. counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 63. input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 64. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 65. output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 66. output compare timing diagram, ftimer = fcpu/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 67. output compare timing diagram, ftimer = fcpu/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 68. one pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 36 figure 69. pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 70. serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 figure 71. single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 72. generic ss timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 73. hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 74. data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 75. clearing the wcol bit (wri te collision flag) so ftware sequence . . . . . . . . . . . . . . . . . . . . 152 figure 76. single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 77. sci block diagram (in conventional baud rate generator mode). . . . . . . . . . . . . . . . . . . . 160 figure 78. word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 79. sci baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 80. lin characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 81. sci block diagram in lin slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 figure 82. lin header reception timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 83. lin synch field measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 84. ldiv read / write operations when ldum = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 85. ldiv read / write operations when ldum = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 86. bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 87. lsf bit set and clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 88. sci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 89. word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 figure 90. sci baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 91. sci example of synchronous and asynchronous transmission . . . . . . . . . . . . . . . . . . . . 206 figure 92. sci data clock timing diagram (m = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 93. sci data clock timing diagram (m = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 94. can network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 95. can block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 96. becan operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 97. becan in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 98. becan in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 99. becan in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 figure 100. transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 list of figures st72561-auto 18/324 doc id 12370 rev 8 figure 101. receive fifo states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 102. filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 103. filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 104. can error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 figure 105. bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 figure 106. can frames (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 107. can frames (part 2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 108. event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 figure 109. fifo corruption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 figure 110. workaround 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 figure 111. critical window timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 figure 112. reception of a sequence of frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 figure 113. reception at maximum can baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 114. workaround 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 115. can register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 figure 116. page mapping for can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 figure 117. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 figure 118. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 figure 119. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 figure 120. fcpu maximum vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 figure 121. lvd startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 figure 122. typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 123. typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 280 figure 124. pll jitter vs signal frequency (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figure 125. awu oscillator freq. @ ta 25c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 figure 126. connecting unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 figure 127. rpu vs vdd with vin = vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 87 figure 128. ipu vs vdd with vin = vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 figure 129. typical vol at vdd = 5v (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 figure 130. typical vol at vdd = 5v (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 figure 131. typical voh at vdd = 5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 figure 132. typical vol vs vdd (standard i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 89 figure 133. typical vol vs vdd (high-sink i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 figure 134. typical voh vs vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 figure 135. reset pin protection when lvd is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 figure 136. reset pin protection when lvd is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 figure 137. reset rpu vs vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 figure 138. two typical applicat ions with iccsel/vpp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 figure 139. spi slave timing diagram with cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 figure 140. spi slave timing diagram with cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 figure 141. spi master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 figure 142. rain max vs fadc with cain = 0pf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 figure 143. recommended cain/rain values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 figure 144. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 figure 145. power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 figure 146. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 figure 147. 64-pin low profile quad flat package (14x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 figure 148. 32-pin low profile quad flat package (7x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 03 figure 149. 44-pin low profile quad flat package (10x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 figure 150. 64-pin low profile quad flat package (10 x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 figure 151. pin 1 orientation in tape and reel conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 figure 152. st72f561xx-auto flash commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . 310 st72561-auto list of figures doc id 12370 rev 8 19/324 figure 153. st72p561xxx-auto fastrom commercial product structure . . . . . . . . . . . . . . . . . . . . . . 311 figure 154. st72561xx-auto rom commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 figure 155. header reception event sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 figure 156. linsci interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 description st72561-auto 20/324 doc id 12370 rev 8 1 description the st72561xx-auto devices are members of the st7 microcontroller family designed for automotive mid-range applications with can (controller area network) and lin (local interconnect network) interface. all devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with flash or rom program memory. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling th e design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. table 2. product overview features st72561(ar/r/j/k)9 s t72561(ar/r/j/k)7 s t72561(ar/r/j/k)6 s t72561(ar/r/j/k)4 program memory - bytes 60k 48k 32k 16k ram (stack) - bytes 2k (256) 2k (256) 1k (256) 1k (256) operating supply 4.5v to 5.5v cpu frequency external resonator oscillator w/ pllx2/8 mhz maximum temperature range -40c to +125c packages lqfp64 10x10mm (ar), lqfp44 10x10mm (j), lqfp32 7x7mm (k) lqfp64 14x14 (r) st72561-auto description doc id 12370 rev 8 21/324 figure 1. device block diagram 1. on some devices only (see table 2: product overview ) 8-bit core alu address and data bus osc1 osc2 reset port a control ram pa7:0 (8 bits) 1 program (16 - 60 kbytes) memory pll x 2 pwm 8-bit port b port c spi linsci2 pb7:0 (8 bits) 1 pc7:0 (8 bits) 1 osc port d pd7:0 (8 bits) 1 /2 option linsci1 16-bit timer (lin master) (lin master/slave) v ss v dd power supply port e pe7:0 (8 bits) 1 port f pf7:0 (8 bits) 1 timer art mcc (clock control) tli 1 watchdog window can (2.0b active) (1 - 2 kbytes) description st72561-auto 22/324 doc id 12370 rev 8 1.1 pin description figure 2. lqfp 64-pin package pinout ain15 / pe3 iccdata / ain1 / pb5 (*)t16_ocmp1 / ain2 / pb6 v ss_2 v dd_2 (*)t16_ocmp2 / ain3 / pb7 (*)t16_icap1 / ain4 / pc0 (*)t16_icap2 / (hs) pc1 t16_extclk / (hs) pc2 pe4 nc iccsel/v pp ain12 / pe0 ain13 / pe1 iccclk / ain0 / pb4 ain14 / pe2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pwm1 / (hs) pa2 pwm2 / pa3 pwm3 / pa4 v ss_3 v dd_3 artclk / (hs)pa5 artic2 / (hs) pa6 t8_ocmp2 / pa7 t8_icap2 / pb0 t8_ocmp1 / pb1 t8_icap1 / pb2 mco / pb3 osc1 osc2 artic1 / pa0 pwm0 / pa1 pf0 pe7 pd0 / spi_ss / ain6 v dd_1 v ss_1 pc7 / spi_sck pc6 / spi_mosi pc5 / spi_miso pe6 / ain5 pe5 pc4 / can_tx pc3 / can_rx pd2 / linsci1_tdo pd1 / linsci1_rdi pf2 / ain8 pf1 / ain7 reset pd5 / linsci2_tdo v dd_0 v dda v ss_0 v ssa pd4 / linsci2_rdi pd3 (hs)/ linsci2_sck pf5 tli pf4 pf3 / ain9 pf7 pf6 pd7 / ain11 pd6 / ain10 ei0 (hs) 20ma high sink capability eix associated external interrupt vector ei3 ei1 ei1 ei3 ei3 ei2 ei3 ei0 ei1 (*) : by option bit: t16_icap2 can be moved to pd1 t16_ocmp1 can be moved to pd3 t16_ocmp2 can be moved to pd5 t16_icap1 can be moved to pd4 st72561-auto description doc id 12370 rev 8 23/324 figure 3. lqfp 44-pin package pinout v ss_2 v dd_2 (*)t16_ocmp2 / ain3 / pb7 (*)t16_icap1 / ain4 / pc0 (*)t16_icap2 / (hs) pc1 t16_extclk / (hs) pc2 pe4 iccsel/vpp iccclk / ain0 / pb4 iccdata / ain1 / pb5 (*)t16_ocmp1 / ain2 / pb6 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 pwm2 / pa3 pwm3 / pa4 artclk / (hs)pa5 artic2 / (hs) pa6 t8_ocmp1 / pb1 t8_icap1 / pb2 mco / pb3 osc1 osc2 pwm0 / pa1 pwm1 / (hs) pa2 pd0 / spi_ss / ain6 pc7 / spi_sck pc6 / spi_mosi pc5 / spi_miso pe6 / ain5 pc4 / can_tx pc3 / can_rx pd2 / linsci1_tdo pd1 / linsci1_rdi pf2 / ain8 pf1 / ain7 v dd_0 v dda v ss_0 v ssa pd4 / linsci2_rdi pd3 (hs) / linsci2_sck pf5 pd7 / ain11 pd6 / ain10 reset pd5 / linsci2_tdo 1 (hs) 20ma high sink capability eix associated external interrupt vector ei0 ei3 ei3 ei1 ei3 ei1 ei2 ei3 (*) : by option bit: t16_icap2 can be moved to pd1 t16_ocmp1 can be moved to pd3 t16_ocmp2 can be moved to pd5 t16_icap1 can be moved to pd4 description st72561-auto 24/324 doc id 12370 rev 8 figure 4. lqfp 32-pin package pinout for external pin connection guidelines, refer to chapter 20: electrical characteristics . t16_ocmp2 / ain3 / pb7 t16_icap1 / ain4 / pc0 t16_icap2 / (hs) pc1 t16_extclk / (hs) pc2 iccsel/v pp iccclk / ain0 / pb4 iccdata / ain1 / pb5 t16_ocmp1 / ain2 / pb6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 101112131415 16 1 2 3 4 5 6 7 8 artclk / (hs) pa5 t8_ocmp1 / pb1 t8_icap1 / pb2 mco / pb3 osc1 osc2 pwm0 / pa1 pwm1 / (hs) pa2 pc6 / spi_mosi pc5 / spi_miso pc4 / can_tx pc3 / can_rx pd2 / linsci1_tdo pd1 / linsci1_rdi pd0 / spi_ss / ain6 pc7 / spi_sck v ss_0 v ssa pd4 / linsci2_rdi pd3 (hs) / linsci2_sck 1 reset pd5 / linsci2_tdo v dd_0 v dda (hs) 20ma high sink capability eix associated external interrupt vector ei0 ei1 ei3 ei3 ei1 ei2 (*) : by option bit: t16_icap2 can be moved to pd1 t16_ocmp1 can be moved to pd3 t16_ocmp2 can be moved to pd5 t16_icap1 can be moved to pd4 st72561-auto description doc id 12370 rev 8 25/324 list of abbreviations used in table 3 type: i = input, o = output, s = supply in/output level: c t = cmos 0.3v dd /0.7v dd with schmitt trigger t t = ttl 0.8v / 2v with schmitt trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog, rb = robust output: od = open drain, pp = push-pull refer to chapter 8: i/o ports for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold which is valid as long as the device is in reset state. table 3. device pin description pin n pin name type level port main function (after reset) alternate function lqfp64 lqfp44 lqfp32 input output input (1) output float wpu int ana od pp 111osc1 (2) i external clock input or resonator oscillator inverter input 222osc2 (2) i/o resonator oscillator inverter output 3 - - pa0 / artic1 i/o c t x ei0 x x port a0 art input capture 1 4 3 3 pa1 / pwm0 i/o c t x ei0 x x port a1 art pwm output 0 5 4 4 pa2 (hs) / pwm1 i/o c t hs x ei0 x x port a2 art pwm output 1 6 5 - pa3 / pwm2 i/o c t x ei0 x x port a3 art pwm output 2 7 6 - pa4 / pwm3 i/o c t x ei0 x x port a4 art pwm output 3 8- -v ss_3 s digital ground voltage 9- -v dd_3 s digital main supply voltage 10 7 5 pa5 (hs) / artclk i/o c t hs x ei0 x x port a5 art external clock 11 8 - pa6 (hs) / artic2 i/o c t hs x ei0 x x port a6 art input capture 2 12 - - pa7 / t8_ocmp2 i/o c t x ei0 x x port a7 tim8 output capture 2 13 - - pb0 /t8_icap2 i/o c t x ei1 x x port b0 tim8 input capture 2 14 9 6 pb1 /t8_ocmp1 i/o c t x ei1 x x port b1 tim8 output capture 1 15 10 7 pb2 / t8_icap1 i/o c t x ei1 x x port b2 tim8 input capture 1 16 11 8 pb3 / mco i/o c t x ei1 x x port b3 main clock out (f osc2 ) 17 - - pe0 / ain12 i/o t t x x rb x x port e0 adc analog input 12 18 - - pe1 / ain13 i/o t t x x rb x x port e1 adc analog input 13 19 12 9 pb4 / ain0 / iccclk i/o c t x ei1 rb x x port b4 icc clock input adc analog input 0 description st72561-auto 26/324 doc id 12370 rev 8 20 - - pe2 / ain14 i/o t t x x rb x x port e2 adc analog input 14 21 - - pe3 / ain15 i/o t t x x rb x x port e3 adc analog input 15 22 13 10 pb5 / ain1 / iccdata i/o c t xei1rbxxport b5 icc data input adc analog input 1 23 14 11 pb6 / ain2 / t16_ocmp1 i/o c t xx rbx x port b6 tim16 output compare 1 adc analog input 2 24 15 - v ss_2 s digital ground voltage 25 16 - v dd_2 s digital main supply voltage 26 17 12 pb7 /ain3 / t16_ocmp2 i/o c t xx rbx x port b7 tim16 output compare 2 adc analog input 3 27 18 13 pc0 / ain4 / t16_icap1 i/o c t xx rbx x port c0 tim16 input capture 1 adc analog input 4 28 19 14 pc1 (hs) / t16_icap2 i/o c t hs x ei2 x x port c1 tim16 input capture 2 29 20 15 pc2 (hs) / t16_extclk i/o c t hs x ei2 x x port c2 tim16 external clock input 30 21 - pe4 i/o t t xx x x port e4 31 - - nc not connected 32 22 16 v pp i flash programming voltage.must be tied low in user mode 33 23 17 pc3 / canrx i/o c t x x x x port c3 can receive data input 34 24 18 pc4 / cantx i/o c t xx (3) port c4 can transmit data output 35 - - pe5 i/o t t xx x x port e5 36 25 - pe6 / ain5 i/o t t x x x x x port e6 adc analog input 5 37 26 19 pc5 /miso i/o c t x x x x port c5 spi master in/slave out 38 27 20 pc6 / mosi i/o c t x x x x port c6 spi master out/slave in 39 28 21 pc7 /sck i/o c t x x x x port c7 spi serial clock 40 - - v ss_1 s digital ground voltage 41 - - v dd_1 s digital main supply voltage 42 29 22 pd0 / ss / ain6 i/o c t xei3 xxxport d0 spi slave select adc analog input 6 table 3. device pin description (continued) pin n pin name type level port main function (after reset) alternate function lqfp64 lqfp44 lqfp32 input output input (1) output float wpu int ana od pp st72561-auto description doc id 12370 rev 8 27/324 43 - - pe7 i/o t t xx x x port e7 44 - - pf0 i/o t t xx x x port f0 45 30 - pf1 / ain7 i/o t t x x x x x port f1 adc analog input 7 46 31 - pf2 / ain8 i/o t t x x x x x port f2 adc analog input 8 47 32 23 pd1 / sci1_rdi i/o c t x ei3 x x port d1 linsci1 receive data input 48 33 24 pd2 / sci1_tdo i/o c t xx x x port d2 linsci1 transmit data output 49 - - pf3 / ain9 i/o t t x x x x x port f3 adc analog input 9 50 - - pf4 i/o t t xx x x port f4 51 - - tli i c t x x top level interrupt input pin 52 34 - pf5 i/o t t xx x x port f5 53 35 25 pd3 (hs) / sci2_sck i/o c t hs x x x x port d3 linsci2 serial clock output 54 36 26 pd4 / sci2_rdi i/o c t x ei3 x x port d4 linsci2 receive data input 55 37 27 v ssa s analog ground voltage 56 38 28 v ss_0 s digital ground voltage 57 39 29 v dda i analog reference voltage for adc 58 40 30 v dd_0 s digital main supply voltage 59 41 31 pd5 / sci2_tdo i/o c t xx x x port d5 linsci2 transmit data output 60 42 32 reset i/o c t top priority non maskable interrupt. 61 43 - pd6 / ain10 i/o c t x ei3 x x x port d6 adc analog input 10 62 44 - pd7 / ain11 i/o c t x ei3 x x x port d7 adc analog input 11 63 - - pf6 i/o t t xx x x port f6 64 - - pf7 i/o t t xx x x port f7 1. in the interrupt input column, ?eix? defines the associated ex ternal interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), t hen the i/o configuration is pull-up interrupt input, else the configuration is floati ng interrupt input. 2. osc1 and osc2 pins connect a crystal /ceramic resonator, or an external so urce to the on-chip oscillator; see chapter 1: description and section 20.5: clock and timing characteristics for more details. 3. input mode can be used for general purpose i/o, output mode only for cantx. on the chip, each i/o port has eight pads. pads that are not bonded to external pins are in input pull-up configuration after reset. the configuration of these pads must be kept at reset state to avoid added current consumption. table 3. device pin description (continued) pin n pin name type level port main function (after reset) alternate function lqfp64 lqfp44 lqfp32 input output input (1) output float wpu int ana od pp register and memory map st72561-auto 28/324 doc id 12370 rev 8 2 register and memory map as shown in figure 5 , the mcu is capable of addressing 64 kbytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, up to 2 kbytes of ram and up to 60 kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh.the highest address bytes contain the user reset and interrupt vectors. caution: memory locations marked as ?reserved? mu st never be accessed . accessing a reserved area can have unpredictable effects on the device. figure 5. memory map 0000h ram program memory (60k, 48k, 32k, 16k) interrupt & reset vectors hw registers 0080h 007fh 0fffh (see ta bl e 4 ) 1000h ffdfh ffe0h ffffh (see ta bl e 1 6 ) 0880h reserved 087fh short addressing ram (zero page) 256 bytes stack 16-bit addressing ram 0100h 01ffh 0080h 0200h 00ffh 1000h 32 kbytes 60 kbytes ffdfh 8000h or 087fh 16 kbytes c000h 48 kbytes 4000h (2048/1024 bytes) 047fh table 4. hardware register map address block register label register name reset status remarks (1) 0000h 0001h 0002h port a pa d r paddr pao r port a data register port a data direction register port a option register 00h (2) 00h 00h r/w (3) r/w (3) r/w (3) 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h (2) 00h 00h r/w (3) r/w (3) r/w (3) 0006h 0007h 0008h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h (2) 00h 00h r/w (3) r/w (3) r/w (3) 0009h 000ah 000bh port d pddr pdddr pdor port d data register port d data direction register port d option register 00h (2) 00h 00h r/w (3) r/w (3) r/w (3) 000ch 000dh 000eh port e pedr peddr peor port e data register port e data direction register port e option register 00h (2) 00h 00h r/w (3) r/w (3) r/w (3) st72561-auto register and memory map doc id 12370 rev 8 29/324 000fh 0010h 0011h port f pfdr pfddr pfor port f data register port f data direction register port f option register 00h (2) 00h 00h r/w (3) r/w (3) r/w (3) 0012h to 0020h reserved area (15 bytes) 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 0024h flash fcsr flash control/status register 00h r/w 0025h 0026h 0027h 0028h 0029h 002ah itc ispr0 ispr1 ispr2 ispr3 eicr0 eicr1 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 external interrupt control register 0 external interrupt control register 1 ffh ffh ffh ffh 00h 00h r/w r/w r/w r/w r/w r/w 002bh 002ch awu awucsr awupr auto wake up f. halt control/status register auto wake up from halt prescaler 00h ffh r/w r/w 002dh 002eh ckctrl sicsr mccsr system integrity control / status register main clock control / status register 0xh 00h r/w r/w 002fh 0030h wwdg wdgcr wdgwr watchdog control register watchdog window register 7fh 7fh r/w r/w 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh pwm art pwmdcr3 pwmdcr2 pwmdcr1 pwmdcr0 pwmcr artcsr artcar artarr articcsr articr1 articr2 pulse width modulator duty cycle register 3 pwm duty cycle register 2 pwm duty cycle register 1 pwm duty cycle register 0 pwm control register auto-reload timer control/status register auto-reload timer counter access register auto-reload timer auto-reload register art input capture cont rol/status register art input capture register 1 art input capture register 2 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only 003ch 003dh 003eh 003fh 0040h 0041h 0042h 0043h 0044h 8-bit timer t8cr2 t8cr1 t8csr t8ic1r t8oc1r t8ctr t8actr t8ic2r t8oc2r timer control register 2 timer control register 1 timer control/status register timer input capture 1 register timer output compare 1 register timer counter register timer alternate counter register timer input capture 2 register timer output compare 2 register 00h 00h 00h xxh 00h fch fch xxh 00h r/w r/w read only read only r/w read only read only read only r/w 0045h 0046h 0047h adc adccsr adcdrh adcdrl control/status register data high register data low register 00h 00h 00h r/w read only read only table 4. hardware register map (continued) address block register label register name reset status remarks (1) register and memory map st72561-auto 30/324 doc id 12370 rev 8 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh linsci1 (lin master/slave) sci1isr sci1dr sci1brr sci1cr1 sci1cr2 sci1cr3 sci1erpr sci1etpr sci1 status register sci1 data register sci1 baud rate register sci1 control register 1 sci1 control register 2 sci1control register 3 sci1 extended receive prescaler register sci1 extended transmit prescaler register c0h xxh 00h xxh 00h 00h 00h 00h read only r/w r/w r/w r/w r/w r/w r/w 0050h reserved area (1 byte) 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh 16-bit timer t16cr2 t16cr1 t16csr t16ic1hr t16ic1lr t16oc1hr t16oc1lr t16chr t16clr t16achr t16aclr t16ic2hr t16ic2lr t16oc2hr t16oc2lr timer control register 2 timer control register 1 timer control/status register timer input capture 1 high register timer input capture 1 low register timer output compare 1 high register timer output compare 1 low register timer counter high register timer counter low register timer alternate counter high register timer alternate counter low register timer input capture 2 high register timer input capture 2 low register timer output compare 2 high register timer output compare 2 low register 00h 00h 00h xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h linsci2 (lin master) sci2sr sci2dr sci2brr sci2cr1 sci2cr2 sci2cr3 sci2erpr sci2etpr sci2 status register sci2 data register sci2 baud rate register sci2 control register 1 sci2 control register 2 sci2 control register 3 sci2 extended receive prescaler register sci2 extended transmit prescaler register c0h xxh 00h xxh 00h 00h 00h 00h read only r/w r/w r/w r/w r/w r/w r/w table 4. hardware register map (continued) address block register label register name reset status remarks (1) st72561-auto register and memory map doc id 12370 rev 8 31/324 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh active can cmcr cmsr ctsr ctpr crfr cier cdgr cpsr can master control register can master status register can transmit status register can transmit priority register can receive fifo register can interrupt enable register can diagnosis register can page selection register r/w r/w r/w r/w r/w r/w r/w r/w 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh pag e s page register 0 page register 1 page register 2 page register 3 page register 4 page register 5 page register 6 page register 7 page register 8 page register 9 page register 10 page register 11 page register 12 page register 13 page register 14 page register 15 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 1. x = undefined, r/w = read/write 2. the contents of the i/o port dr registers are readable only in output conf iguration. in input confi guration, the values of th e i/o pins are returned instead of the dr register contents. 3. the bits associated with unavailable pi ns must always keep their reset value. table 4. hardware register map (continued) address block register label register name reset status remarks (1) flash program memory st72561-auto 32/324 doc id 12370 rev 8 3 flash program memory 3.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 3.2 main features 3 flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be programmed or erased. ? icp (in-circuit programming). in this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. ? iap (in-application programming) in this mode, all sectors except sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ict (in-circuit testing) for downloading and executing user application test patterns in ram read-out protection register access security system (rass) to prevent accidental programming or erasing 3.3 structure the flash memory is organized in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see ta b l e 5 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flas h memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 6 ). they are mapped in the upper part of the st7 addressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). table 5. sectors available in flash devices flash size (bytes) available sectors 4k sector 0 8k sectors 0,1 > 8k sectors 0,1, 2 st72561-auto flas h program memory doc id 12370 rev 8 33/324 3.3.1 read-out protection read-out protection, when selected, provides a protection against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. in flash devices, this protection is removed by reprogramming the option. in this case, the entire program memory is first automatically erased and the device can be reprogrammed. read-out protection selection depends on the device type: in flash devices it is enabled and removed through the fmp_r bit in the option byte. in rom devices it is enabled by mask option specified in the option list. figure 6. memory map and sector address 3.4 icc interface icc (in-circuit communication) needs a minimum of four and up to six pins to be connected to the programming tool (see figure 7 ). these pins are: reset : device reset v ss : device power supply ground iccclk: icc output serial clock pin iccdata: icc input/output serial data pin iccsel/v pp : programming voltage osc1(or oscin): main clock input for external source (optional) v dd : application board power supply (see figure 7 , note 3) 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k flash ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes memory size 8kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k flash program memory st72561-auto 34/324 doc id 12370 rev 8 figure 7. typical icc interface note: 1 if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programmin g tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. refer to the programming tool documentation for recommended resistor values. 2 during the icc session, the progra mming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor < 1k). a schottky diode can be used to isolate the application reset circuit in this case. when using a classical rc network with r > 1k or a reset management ic with open drain output and pull-up resistor > 1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3 the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st programming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4 pin 9 has to be connected to the osc1 or oscin pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. st7 devices with multi-oscillator capabilit y need to have osc2 grounded in this case. 3.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-cir cuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the specific microcontroller device, the user needs only to implement the icp hardware icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) 10k v ss iccsel/vpp st7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 application reset source application i/o (see note 4) st72561-auto flas h program memory doc id 12370 rev 8 35/324 interface on the application board (see figure 7 ). for more details on the pin locations, refer to the device pinout description. 3.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the spi, sci or other type of serial interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 3.7 related documentation for details on flash programming and icc protocol, refer to the st7 flash programming reference manual and to the st7 icc protocol reference manual . 3.8 register description flash control/status register (fcsr) read/ write reset value: 0000 0000 (00h) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. 7 0 00000000 table 6. flash control/status register address and reset value address (hex.) register label 76543210 0024h fcsr reset value 00000000 central processing unit st72561-auto 36/324 doc id 12370 rev 8 4 central processing unit 4.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 4.2 main features enable executing 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) two 8-bit index registers 16-bit stack pointer low power halt and wait modes priority maskable hardware interrupts non-maskable software/hardware interrupts 4.3 cpu registers the six cpu registers shown in figure 8 are not present in the memory mapping and are accessed by specific instructions. 4.3.1 accumulator (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 4.3.2 index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register.) the y register is not affected by the interrupt automatic procedures. 4.3.3 program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). st72561-auto central processing unit doc id 12370 rev 8 37/324 figure 8. cpu registers 4.3.4 condition code register (cc) read/ write reset value: 111x1xxx the 8-bit condition code register contains the interrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. these bits can be individually tested and/or controlled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jr h or jrnh instruction. the h bit is useful in bcd arithmetic subroutines. bit 2 = n negative . this bit is set and cleared by hardware. it is re presentative of the result sign of the last arithmetic, logical or data manipulation. it?s a copy of the result 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (that is, the most significant bit is a logic 1). accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 1 1 x1 xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 7 0 11i1hi0nzc central processing unit st72561-auto 38/324 doc id 12370 rev 8 this bit is accessed by the jrmi and jrpl instructions. bit 1 = z zero . this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf in structions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the current interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (ixspr). they can be also set/cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. table 7. interrupt software priority selection interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 st72561-auto central processing unit doc id 12370 rev 8 39/324 4.3.5 stack pointer (sp) read/ write reset value: 01 ffh the stack pointer is a 16-bit register which is always pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 9 ). since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 9 . when an interrupt is received, the sp is decremented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an interrupt five locations in the stack area. 15 8 00000001 7 0 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 central processing unit st72561-auto 40/324 doc id 12370 rev 8 figure 9. stack manipulation example pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h st72561-auto supply, reset and clock management doc id 12370 rev 8 41/324 5 supply, reset and clock management 5.1 introduction the device includes a range of utility featur es for securing the application in critical situations (for example, in case of a power brown-out), and reducing the number of external components. an overview is shown in figure 11 . for more details, refer to dedicated parametric section. 5.2 main features optional pll for multiplying the frequency by 2 reset sequence manager (rsm) multi-oscillator clock management (mo) ? 4 crystal/ceramic resonator oscillators system integrity management (si) ? main supply low voltage detection (lvd) ? auxiliary voltage detector (avd) with inte rrupt capability for monitoring the main supply 5.3 phase locked loop if the clock frequency input to the pll is in the range 2 to 4 mhz, the pll can be used to multiply the frequency by two to obtain an f osc2 of 4 to 8 mhz. the pll is enabled by option byte. if the pll is disabled, then f osc2 =f osc /2. caution: the pll is not recommended for applications where timing accuracy is required. section 20.5.2: pll characteristics figure 10. pll block diagram 0 1 pll option bit pll x 2 f osc2 / 2 f osc supply, reset and clock management st72561-auto 42/324 doc id 12370 rev 8 figure 11. clock, reset and supply block diagram 5.4 multi-oscillator (mo) the main clock of the st7 can be generated by two different source types coming from the multi-oscillator block: an external source a crystal or ceramic resonator oscillator each oscillator is optimized fo r a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configuration are shown in ta bl e 8 . refer to the electrical characteristics section for more details. caution: the osc1 and/or osc2 pins must not be left unconnected. for the purposes of failure mode and effect analysis, it should be noted that if the osc1 and/or osc2 pins are left unconnected, the st7 main oscillator may start a nd, in this configuration, could generate an f osc clock frequency in excess of the allowed maximum (> 16 mhz), putting the st7 in an unsafe/undefined state. the product behavior must therefore be considered undefined when the osc pins are left unconnected. external clock source in external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. crystal/ceramic oscillators this family of oscillators has the advantage of prod ucing a very accurate rate on the main clock of the st7. the selection within a list of five oscillators with di fferent frequency ranges must be done by option byte in order to reduce consumption (refer to section 22.2.1: flash configuration for more details on the frequency ranges). the resonator and the load capacitors must be placed as close as possible to the oscillator pins in order to minimize low voltage detector (lvd) auxiliary voltage detector (avd) multi- oscillator (mo) osc1 reset v ss v dd reset sequence manager (rsm) osc2 main clock avd interrupt request controller pll system integrity management watchdog sicsr timer (wdg) with realtime clock (mcc/rtc) avd avd lvd rf ie wdg rf f osc f osc2 (option) 0 0 f f cpu 00 8-bit timer / 8000 st72561-auto supply, reset and clock management doc id 12370 rev 8 43/324 output distortion and start-up stabilization time. the loading capacitance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. 5.5 reset sequence manager (rsm) 5.5.1 introduction the reset sequence manager includes three reset sources as shown in figure 13 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset these sources act on the reset pin and it is always kept low during the delay phase. the reset service routine vector is fixed at addresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of three phases as shown in figure 12 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (selected by option byte) reset vector fetch the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the reset stat e. the shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. table 8. st7 clock sources hardware configuration external clock crystal/ceramic resonators osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 supply, reset and clock management st72561-auto 44/324 doc id 12370 rev 8 the reset vector fetch phase duration is two clock cycles. figure 12. reset sequence phases 5.5.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. see chapter 20: electrical characteristics for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 14 ). this detection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 13. reset block diagram the reset pin is an asynchronous sign al which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 5.5.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specif ied for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc network connected to the reset pin. 5.5.4 internal low voltage detector (lvd) reset two different reset sequences caused by the internal lvd circuitry can be distinguished: power-on reset voltage drop reset reset active phase internal reset 256 or 4096 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter st72561-auto supply, reset and clock management doc id 12370 rev 8 45/324 the device reset pin acts as an output that is pulled low when v dd st72561-auto supply, reset and clock management doc id 12370 rev 8 47/324 if t rv is greater than 256 or 4096 cycles then: if the avd interrupt is enabled before the v it+(avd) threshold is reached, then two avd interrupts will be received: the first when the avdie bit is set and the second when the threshold is reached. if the avd interrupt is enabled after the v it+(avd) threshold is reached, then only one avd interrupt occurs. figure 16. using the avd to monitor v dd 5.6.3 low power modes 5.6.4 interrupts the avd interrupt event generates an interrupt if the avdie bit is set and the interrupt mask in the cc register is re set (rim instruction). v dd v it+(avd) v it-(avd) avdf bit 0 0 reset value if avdie bit = 1 v hyst avd interrupt request interrupt process interrupt process v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 1 1 t rv voltage rise time table 9. effect of low power modes on si mode description wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the sicsr register is frozen. table 10. interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no supply, reset and clock management st72561-auto 48/324 doc id 12370 rev 8 5.6.5 register description system integrity (si) control/status register (sicsr) read/write reset value: 000x 000x (00h) bit 7 = reserved, must be kept cleared. bit 6 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag changes (toggles). the pending interrupt information is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled bit 5 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is generated when the avdf bit changes value. refer to figure 16 and to monitoring the vdd main supply for additional details. 0: v dd over v it+(avd) threshold 1: v dd under v it-(avd) threshold bit 4 = lvdrf lvd reset flag this bit indicates that the last reset was generated by the lvd block. it is set by hardware (lvd reset) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bits 3:1 = reserved, must be kept cleared. bit 0 = wdgrf watchdog reset flag this bit indicates that the last reset was generated by the watchdog peripheral. it is set by hardware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. 7 0 0 avdie avdf lvdrf 0 0 0 wdgrf st72561-auto supply, reset and clock management doc id 12370 rev 8 49/324 application notes the lvdrf flag is not cleared when another reset ty pe occurs (external or watchdog), the lvdrf flag remains set to keep trace of the original failure. in this case, a watchdog reset can be detected by software while an external reset can not. caution: when the lvd is not activated with the associated option byte, the wdgrf flag cannot be used in the application. table 11. reset source flags reset sources lvdrf wdgrf external reset pin 0 0 watchdog 1 lv d 1 x interrupts st72561-auto 50/324 doc id 12370 rev 8 6 interrupts 6.1 introduction the st7 enhanced interrupt management provides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrupt priority and level management: ? up to 4 software programmable nesting levels ? up to 16 interrupt vectors fixed by hardware ? 2 non maskable events: reset, trap ? 1 maskable top level event: tli this interrupt management is based on: bit 5 and bit 3 of the cpu cc register (i1:0), interrupt software priority registers (isprx), fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced in terrupt controller guarant ees full upward compatib ility with the standard (not nested) st7 interrupt controller. 6.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see ta bl e 1 2 ). the processing flow is shown in figure 17 . when an interrupt request has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to ?interrupt mapping? table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, th e i1 and i0 bits will be restored from the stack and the program in the pr evious level will resume. st72561-auto interrupts doc id 12370 rev 8 51/324 figure 17. interrupt processing flowchart servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. figure 18 describes this decision process. figure 18. priority decision process table 12. interrupt software priority levels interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 level 3 (= interrupt disable) 1 1 ?iret? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset tli pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt pending software different interrupts same highest hardware priority serviced priority highest software priority serviced interrupts st72561-auto 52/324 doc id 12370 rev 8 when an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. note: 1 the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. 2 reset, trap and tli can be considered as havi ng the highest software priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, trap) and the maskable type (e xternal or from in ternal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 17 ). after stacking the pc, x, a and cc registers (except for reset), the corresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. trap (non maskable software interrupt) caution: this software interrupt is serv iced when the trap instruction is executed. it will be serviced according to the flowchart in figure 17 as a tli. trap can be interrupted by a tli. reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the highest hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if an y of these two conditions is false, the interrupt is latched and thus remains pending. tli (top level hardware interrupt) caution: this hardware interrupt occurs when a specific edge is detected on the dedicated tli pin. a trap instruction must not be used in a tli service routine. external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the external interrupt control register (eicr). external interrupt triggered on edge will be la tched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the ?interrupt mapping? table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and st72561-auto interrupts doc id 12370 rev 8 53/324 if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note: the clearing sequence resets the internal latch. a pending interrupt (that is, waiting for being serviced) will theref ore be lost if the clea r sequence is executed. 6.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column ?exit from halt? in ?interrupt mapping? table). when several pending interrupts are present while exiting halt mode, the first one serviced can only be an interrupt with exit from halt mode capability and it is selected through the same decision process shown in figure 18 . note: if an interrupt, that is not able to exit fr om halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 6.4 concurrent & nested management the following figure 19 and figure 20 show two different interrupt management modes. the first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in figure 20 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning: a stack overflow may occur without notifying the software of the failure. figure 19. concurrent interrupt management main it4 it2 it1 tli it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 tli it3 it0 it3 i0 10 priority level used stack = 10 bytes interrupts st72561-auto 54/324 doc id 12370 rev 8 figure 20. nested interrupt management 6.5 interrupt register description 6.5.1 cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop instructions (see table 15: dedicated interrupt instruction set on page 55 ). main it2 tli main it0 it2 it1 it4 tli it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes 7 0 11i1hi0nzc table 13. interrupt software priority levels interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 level 3 (= interrupt disable (1) ) 1. tli, trap and reset events can interrupt a level 3 program. 11 st72561-auto interrupts doc id 12370 rev 8 55/324 6.5.2 interrupt software pr iority registers (isprx) read/ write (bit 7:4 of ispr3 are read only) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this correspondence is shown in the following table. each i1_x and i0_x bit value in the isprx registers has the same meaning as the i1 and i0 bits in the cc register. level 0 cannot be written (i1_x = 1, i0_x = 0). in this case, the previously stored value is kept (example: previous = cfh, write = 64h, result = 44h) the reset, trap and tli vectors have no software priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. caution: if the i1_x and i0_x bits are modified while the interrupt x is executed the following behavior has to be considered: if the inte rrupt x is still pending (new inte rrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the interrupt x). 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 table 14. interrupt priority bits vector address isprx bits fffbh-fffah i1_0 and i0_0 bits (1) 1. bits in the isprx registers which correspond to the tli can be read and written but they are not significant in the interrupt process management. fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits table 15. dedicated interrupt instruction set instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0 = 11 (level 3) i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11? interrupts st72561-auto 56/324 doc id 12370 rev 8 note: during the execution of an interrupt routine, the halt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruction or one of the previously mentioned instruction pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 table 15. dedicated interrupt instruction set (continued) instruction new description function/example i1 h i0 n z c st72561-auto interrupts doc id 12370 rev 8 57/324 table 16. interrupt mapping n source block description register label priority order exit from halt (1) address vector reset reset n/a highest priority lowest priority yes fffeh- ffffh trap software interrupt no fffch- fffdh 0 tli external top level interrupt eicr yes fffah- fffbh 1 mcc/rtc main clock controller time base interrupt mccsr yes fff8h-fff9h 2 ei0/awufh external interrupt ei0/ auto wake-up from halt eicr/aw ucsr yes (2) fff6h-fff7h 3ei1/avd external interrupt ei1/auxiliary voltage detector eicr/ sicsr fff4h-fff5h 4 ei2 external interrup t ei2 eicr fff2h-fff3h 5 ei3 external interrup t ei3 eicr fff0h-fff1h 6 can can peripheral interrupt - rx cier no ffeeh- ffefh 7 can can peripheral interrupt - tx / er / sc cier yes (3) ffech- ffedh 8 spi spi peripheral interrupts spicsr yes ffeah- ffebh 9 timer8 8-bit timer peripheral interrupts t8_tcr1 no ffe8h- ffe9h 10 timer16 16-bit timer peripheral interrupts tcr1 no ffe6h- ffe7h 11 linsci2 linsci2 peripheral interrupts sci2cr1 no ffe4h- ffe5h 12 linsci1 linsci1 peripheral interrupts (lin master/slave) sci1cr1 no (4) ffe2h- ffe3h 13 pwm art 8-bit pwm art interrupts pwmcr yes ffe0h- ffe1h 1. valid for halt and active halt modes except for the mcc/ rtc interrupt source which ex its from active halt mode only. 2. except avd interrupt. 3. exit from halt only when a wake-up condition is detected, generating a status change interrupt. see section 16.6: interrupts . 4. t is possible to exit from halt using the external interrupt which is mapped on the rdi pin. interrupts st72561-auto 58/324 doc id 12370 rev 8 6.6 external interrupts 6.6.1 i/o port in terrupt sensitivity the external interrupt sensitivity is controlled by the isxx bits in the eicr register ( figure 21 ). this control allows up to four fully independent external interrupt source sensitivities. each external interrupt source can be generated on four (or five) different events on the pin: falling edge rising edge falling and rising edge falling edge and low level to guarantee correct functionality, the sensitivity bits in the eicr register can be modified only when the i1 and i0 bits of the cc register are both set to 1 (level 3). this means that interrupts must be disabled before changing sensitivity. the pending interrupts are cleared by writing a different value in the isx[1:0] of the eicr. st72561-auto interrupts doc id 12370 rev 8 59/324 figure 21. external interrupt control bits is10 is11 eicr sensitivity control pbor.0 pbddr.0 pb0 ei1 interrupt source port b [5:0] interrupts pb0 pb1 pb2 pb3 is20 is21 eicr sensitivity control pcor.7 pcddr.7 pc1 ei2 interrupt source port c [2:1] interrupts pc1 pc2 is00 is01 eicr sensitivity control paor.0 paddr.0 pa0 ei0 interrupt source port a [7:0] interrupts pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 / awupr awufh oscillator to timer input capture 1 pb4 pb5 is30 is31 eicr sensitivity control pdor.0 pdddr.0 pd0 ei3 interrupt source port d [7:6, 4, 1:0] interrupts pd0 pd1 pd4 pd6 pd7 interrupts st72561-auto 60/324 doc id 12370 rev 8 6.6.2 register description external interrupt control register 0 (eicr0) read/write reset value: 0000 0000 (00h) bits 7:6 = is3[1:0] ei3 sensitivity the interrupt sensitivity, defined using the is3[1:0] bits, is applied to the ei3 external interrupts: these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bits 5:4 = is2[1:0] ei2 sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the ei2 external interrupts: these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bits 3:2 = is1[1:0] ei1 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the ei1 external interrupts: 7 0 is31 is30 is21 is20 is11 is10 is01 is00 table 17. interrupt sensitivity - ei3 is31 is30 external interrupt sensitivity 0 0 falling edge and low level 1 rising edge only 1 0 falling edge only 1 rising and falling edge table 18. interrupt sensitivity - ei2 is21 is20 external interrupt sensitivity 0 0 falling edge and low level 1 rising edge only 1 0 falling edge only 1 rising and falling edge table 19. interrupt sensitivity - ei1 is11 is10 external interrupt sensitivity 0 0 falling edge and low level 1 rising edge only st72561-auto interrupts doc id 12370 rev 8 61/324 these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bits 1:0 = is0[1:0] ei0 sensitivity the interrupt sensitivity, defined using the is0[1:0] bits, is applied to the ei0 external interrupts: these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). external interrupt control register 1 (eicr1) read/write reset value: 0000 0000 (00h) bits 7:2 = reserved bit 1 = tlis top level interrupt sensitivity this bit configures the tli edge sensitivity. it can be set and cleared by software only when tlie bit is cleared. 0: falling edge 1: rising edge bit 0 = tlie top level interrupt enable this bit allows to enable or disable the tli capability on the dedicate d pin. it is set and cleared by software. 0: tli disabled 1: tli enabled note: a parasitic interrupt can be generated when clearing the tlie bit. in some packages, the tli pin is not available. in this case, the tlie bit must be kept low to avoid parasitic tli interrupts. 1 0 falling edge only 1 rising and falling edge table 20. interrupt sensitivity - ei0 is01 is00 external interrupt sensitivity 0 0 falling edge and low level 1 rising edge only 1 0 falling edge only 1 rising and falling edge 7 0 000000tlistlie table 19. interrupt sensitivity - ei1 is11 is10 external interrupt sensitivity interrupts st72561-auto 62/324 doc id 12370 rev 8 table 21. nested interrupts register map and reset values address (hex.) register label 76543210 0025h ispr0 reset value ei1 ei0 clkm tli i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 0026h ispr1 reset value can tx/er/sc can rx ei3 ei2 i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0027h ispr2 reset value linsci 2 timer 16 timer 8 spi i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0028h ispr3 reset value1111 art linsci 1 i1_13 1 i0_13 1 i1_12 1 i0_12 1 0029h eicr0 reset value is31 0 is30 0 is21 0 is20 0 is11 0 is10 0 is01 0 is00 0 002ah eicr1 reset value000000 tlis 0 tlie 0 st72561-auto power saving modes doc id 12370 rev 8 63/324 7 power saving modes 7.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, five main power saving modes are implemented in the st7 (see figure 22 ): slow wait (and slow-wait) active halt auto wake-up from halt (awufh) halt after a reset the normal operating mode is se lected by default (r un mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main osc illator frequency divided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. figure 22. power saving mode transitions 7.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the mccsr register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). power consumption wait slow run active halt high low slow wait auto wake-up from halt halt power saving modes st72561-auto 64/324 doc id 12370 rev 8 in this mode, the master clock frequency (f osc2 ) can be divided by 2, 4, 8 or 16. the cpu and peripherals are clocked at this lower frequency (f cpu ). note: slow-wait mode is activated by entering wait mode while the device is in slow mode. figure 23. slow mode clock transitions 7.3 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i[1:0] bits of the cc register are forced to ?10?, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 24 00 01 sms cp1:0 f cpu new slow normal run mode mccsr frequency request request f osc2 f osc2 /2 f osc2 /4 f osc2 st72561-auto power saving modes doc id 12370 rev 8 65/324 figure 24. wait mode flow-chart note: before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. 7.4 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the ?halt? instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 10: main clock controller with real time clock mcc/rtc for more details on the mccsr register) and when the awuen bit in the awucsr register is cleared. the mcu can exit halt mode on receptio n of either a specific interrupt (see ta bl e 1 6 ) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and t he 256 or 4096 cpu cycle dela y is used to stabilize the oscillator. after the start up de lay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 26 ). when entering halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillator is turned off causing all internal pr ocessing to be stopped, including the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of wa tchdog operation with halt mode is configured by the ?wdghalt? option bit of the option byte. the halt instruction when executed while the watchdog wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 10 on cpu oscillator peripherals i[1:0] bits on on xx 1) on 256 or 4096 cpu clock cycle delay power saving modes st72561-auto 66/324 doc id 12370 rev 8 system is enabled, can gener ate a watchdog reset (see section 22.1: introduction for more details). figure 25. halt timing overview figure 26. halt mode flow-chart note: 1 wdghalt is an option bit. see option byte section for more details. 2 peripheral clocked with an external clock source can still be active. 3 only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to ta bl e 1 6 for more details. 4 before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie=0] reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle halt instruction (mccsr.oie=0) (awucsr.awuen=0) st72561-auto power saving modes doc id 12370 rev 8 67/324 halt mode recommendations make sure that an external event is available to wake up the microcontroller from halt mode. when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitialize the level sens itiveness of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0x8e . to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the interrupt ma sk in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 7.5 active halt mode active halt mode is the lowest power consumption mode of the mcu with a real time clock available. it is entered by executing the ?halt? instruction when mcc/rtc interrupt enable flag (oie bit in mccsr register) is set and when the awuen bit in the awucsr register is cleared ( section 7.6.1: register description ) the mcu can exit active halt mode on reception of the rtc interrupt and some specific interrupts (see ta bl e 1 6 ) or a reset. when exiting active halt mode by means of a reset a 4096 or 256 cpu cycle delay occurs (depending on the op tion byte). after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 28 ). when entering active halt mode, the i[1:0] bits in the cc register are are forced to ?10b? to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active halt mode, only the main oscilla tor and its associated counter (mcc/rtc) are running to keep a wake-up time base. all ot her peripherals are not clocked except those which get their clock supply from another cloc k generator (such as external or auxiliary oscillator). the safeguard against staying locked in active halt mode is provided by the oscillator interrupt. table 22. mcc/rtc low power mode selection mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active halt mode power saving modes st72561-auto 68/324 doc id 12370 rev 8 note: as soon as active halt is enabled, executing a halt instruction while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 27. active halt timing overview figure 28. active halt mode flow-chart note: 1 this delay occurs only if the mcu exits active halt mode by means of a reset. 2 peripheral clocked with an external clock source can still be active. 3 only the rtc interrupt and some specific interrupts can exit the mcu from active halt mode (such as external interrupt). refer to ta b l e 1 6 for more details. 4 before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits in the cc register are set to the current software priority level of the interrupt routine and restored when the cc register is popped. 7.6 auto wake-up from halt mode auto wake-up from halt (awufh) mode is similar to halt mode with the addition of an internal rc oscillator for wake-up. comp ared to active halt mode, awufh has lower power consumption because the main clock is not kept running, but there is no accurate realtime clock available. halt run run 256 or 4096 cycle delay (after reset) reset or interrupt halt instruction fetch vector active (active halt enabled) halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits on off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock cycle delay (mccsr.oie=1) (awucsr.awuen=0) st72561-auto power saving modes doc id 12370 rev 8 69/324 it is entered by executing the halt inst ruction when the awuen bit in the awucsr register has been set and the oie bit in the mccsr register is cleared (see section 10: main clock controller with real time clock mcc/rtc for more details). figure 29. awufh mode block diagram as soon as halt mode is entered, and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divider and a programmable prescaler controlled by the awupr register. the output of this prescaler provides the delay time. when the delay has elapsed the awuf flag is set by hardware and an interrupt wakes up the mcu from halt mode. at the same time the main oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. after this start-up delay, the cpu resumes operation by servicing the awufh interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run mode. this connects f awu_rc to the icap1 input of the 16-bit timer, allowing the f awu_rc to be measured using the main osc illator clock as a reference time base. similarities with halt mode the following awufh mode behavior is the same as normal halt mode: the mcu can exit awufh mode by means of any interrupt with exit from halt capability or a reset (see section 7.4: halt mode ). when entering awufh mode, the i[1:0] bits in the cc register are forced to 10b to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in awufh mode, the main oscilla tor is turned off causing a ll internal processing to be stopped, including the operation of the on-chip peripherals. none of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the awu oscillator). the compatibility of watchdog operation with awufh mode is configured by the wdghalt option bit in the option byte. depending on this setting, the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset. awu rc awufh f awu_rc awufh (ei0 source) oscillator prescaler interrupt /64 divider to timer input capture /1 .. 255 power saving modes st72561-auto 70/324 doc id 12370 rev 8 figure 30. awuf halt timing diagram figure 31. awufh mode flow-chart note: 1 wdghalt is an option bit. see option byte section for more details. 2 peripheral clocked with an external clock source can still be active. 3 only an awufh interrupt and some specific in terrupts can exit the mcu from halt mode (such as external interrupt). refer to ta b l e 1 6 for more details. 4 before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. awufh interrupt f cpu run mode halt mode 256 or 4096 t cpu run mode f awu_rc clear by software t awu reset interrupt 3) y n n y cpu main osc peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx 4) on cpu main osc peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle awu rc osc on awu rc osc off awu rc osc off halt instruction (mccsr.oie=0) (awucsr.awuen=1) st72561-auto power saving modes doc id 12370 rev 8 71/324 7.6.1 register description awufh control/status register (awucsr) read/write (except bit 2 read only) reset value: 0000 0000 (00h) bits 7:3 = reserved. bit 2 = awuf auto wake-up flag this bit is set by hardware when the awu module generates an interrupt and cleared by software on reading awucsr. 0: no awu interrupt occurred 1: awu interrupt occurred bit 1 = awum auto wake-up measurement this bit enables the awu rc oscillator and connec ts its output to the icap1 input of the 16- bit timer. this allows the timer to be used to measure the awu rc oscillator dispersion and then compensate this dispersion by providing the right value in the awupr register. 0: measurement disabled 1: measurement enabled bit 0 = awuen auto wake-up from halt enabled this bit enables the auto wake-up from halt feature: once halt mode is entered, the awufh wakes up the microcontroller after a time delay defined by the awu prescaler value. it is set and cleared by software. 0: awufh (auto wake-up from halt) mode disabled 1: awufh (auto wake-up from halt) mode enabled awufh prescaler register (awupr) read/write reset value: 1111 1111 (ffh) bits 7:0 = awupr[7:0] auto wake-up prescaler these 8 bits define the awupr divi ding factor as explained below: 7 0 0 0 0 0 0 awuf awum awuen 7 0 awupr7 awupr6 awupr5 awupr4 awupr3 awupr2 awupr1 awupr0 table 23. awupr prescaler awupr[7:0 ] dividing factor 00h forbidden (see note) 01h 1 ... ... power saving modes st72561-auto 72/324 doc id 12370 rev 8 in awu mode, the period that the mcu stays in halt mode (t awu in figure 30 ) is defined by this prescaler register can be programmed to modify the time that the mcu stays in halt mode before waking up automatically. note: if 00h is written to awupr, depending on th e product, an interrupt is generated immediately after a halt instruction or the awupr remains unchanged. feh 254 ffh 255 table 23. awupr prescaler (continued) awupr[7:0 ] dividing factor t awu 64 awup 1 t awurc ---------------------- t rcstrt + = table 24. awu register map and reset values address (hex.) register label 76543210 002bh awucsr reset value 00000 awuf 0 awum 0 awuen 0 002ch awupr reset value awupr7 1 awupr6 1 awupr5 1 awupr4 1 awupr3 1 awupr2 1 awupr1 1 awupr0 1 st72561-auto i/o ports doc id 12370 rev 8 73/324 8 i/o ports 8.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 8.2 functional description each port has two main registers: data register (dr) data direction register (ddr) and one optional register: option register (or) each i/o pin may be programmed using the corresponding register bits in the ddr and or registers: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not provide this register refer to the i/o port implementation section). the generic i/o block diagram is shown in figure 32 8.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. note: 1 writing the dr register modifies the latch value but does not affect the pin status. 2 when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3 do not use read/modify/write instructions (bset or bres) to modify the dr register as this might corrupt the dr content for i/os configured as input. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external interrupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the eicr register. i/o ports st72561-auto 74/324 doc id 12370 rev 8 each external interrupt vector is linked to a dedicated group of i/o port pins (see pinout description and interrupt section). if several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the eicr register and then logically ored. the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the eicr register must be modified. 8.2.2 output modes the output conf iguration is selected by setting the co rresponding ddr regist er bit. in this case, writing the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. 8.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digi tally readable by addressing the dr register. note: input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. table 25. dr register value and output pin status dr push-pull open-drain 0v ss vss 1v dd floating st72561-auto i/o ports doc id 12370 rev 8 75/324 figure 32. i/o port general block diagram note: the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the device against positive stress. table 26. i/o port mode options (1) 1. ni - not implemented off - implemented not activated on - implemented and activated configuration mode pull-up p-buffer diodes input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) external source (ei x ) interrupt cmos schmitt trigger register access i/o ports st72561-auto 76/324 doc id 12370 rev 8 caution: the alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected analog pin. table 27. i/o port configurations hardware configuration input (1) 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate function output status. open-drain output (2) 2. when the i/o port is in output configuration and t he associated alternate func tion is enabled as an input, the alternate function reads the pin stat us given by the dr register content. push-pull output 2) condition pad v dd r pu external interrupt data bus pull-up interrupt dr register access w r source ( ei x ) dr register condition alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports st72561-auto i/o ports doc id 12370 rev 8 77/324 warning: the analog input voltage level must be within the limits stated in the absolute maximum ratings. 8.3 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific feature of the i/o port such as adc input or true open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommend ed safe transitions are illustrated in figure 33 . other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 33. interrupt i/o port state transitions 8.4 i/o port register configurations the i/o port register configurations are summarized as follows. 8.4.1 standard ports 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or table 28. configuration of pb7:6, pc0, pc3, pc7:5, pd3:2, pd5, pe7:0, pf7:0 mode ddr or floating input 0 0 pull-up input 1 open drain output 1 0 push-pull output 1 i/o ports st72561-auto 78/324 doc id 12370 rev 8 8.4.2 interrupt ports table 29. configuration of pa0, 2, 4, 6; pb0, 2,4; pc1; pd0,6 (with pull-up) mode ddr or floating input 0 0 pull-up interrupt input 1 open drain output 1 0 push-pull output 1 table 30. configuration of pa1, 3, 5, 7; pb1,3,5; pc2; pd1, 4, 7 (without pull-up) mode ddr or floating input 0 0 floating interrupt input 1 open drain output 1 0 push-pull output 1 st72561-auto i/o ports doc id 12370 rev 8 79/324 8.4.3 pull-up input port (cantx requirement) the pc4 port cannot operate as a general purpose output. the can peripheral controls it directly when enabled. othe rwise, pc4 is a pull-up input. if ddr = 1 it is still possible to read the port through the dr register. table 31. configuration of pc4 mode pull-up input table 32. port configuration port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa 0 floating pull-up interrupt (ei0) open drain push-pull pa1 floating interrupt (ei0) pa2 pull-up interrupt (ei0) pa3 floating interrupt (ei0) pa4 pull-up interrupt (ei0) pa5 floating interrupt (ei0) pa6 pull-up interrupt (ei0) pa7 floating interrupt (ei0) port b pb0 floating pull-up interrupt (ei1) open drain push-pull pb1 floating interrupt (ei1) pb2 pull-up interrupt (ei1) pb3 floating interrupt (ei1) pb4 pull-up interrupt (ei1) pb5 floating interrupt (ei1) port c pc0 floating pull-up open drain push-pull pc1 pull-up interrupt (ei2) pc2 floating interrupt (ei2) pc3 pull-up pc4 pull-up controlled by cantx (1) pc7:5 floating pull-up open drain push-pull i/o ports st72561-auto 80/324 doc id 12370 rev 8 8.5 low power modes 8.6 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). port d pd0 floating pull-up interrupt (ei3) open drain push-pull pd1 floating interrupt (ei3) pd3:2 pull-up pd4 floating interrupt (ei3) pd5 pull-up pd6 pull-up interrupt (ei3) pd7 floating interrupt (ei3) port e pe7:0 floating (ttl) pull-up (ttl) open drain push-pull port f pf7:0 floating (ttl) pull-up (ttl) open drain push-pull 1. when the cantx alternate function is selected, the i/o port operates in output push-pull mode. table 32. port configuration (continued) port pin name input output or = 0 or = 1 or = 0 or = 1 table 33. effect of low power modes on i/o ports mode description wait no effect on i/o ports. external interrup ts cause the device to exit from wait mode. halt no effect on i/o ports. external interrup ts cause the device to exit from halt mode. table 34. i/o port interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx ye s st72561-auto i/o ports doc id 12370 rev 8 81/324 table 35. i/o port register map and reset values address (hex.) register label 76543210 reset value of all io port registers 000 00000 0000h padr msb lsb 0001h paddr 0002h paor 0003h pbdr msb lsb 0004h pbddr 0005h pbor 0006h pcdr msb lsb 0007h pcddr 0008h pcor 0009h pddr msb lsb 000ah pdddr 000bh pdor 000ch pedr msb lsb 000dh peddr 000eh peor 000fh pfdr msb lsb 0010h pfddr 0011h pfor window watchdog (wwdg) st72561-auto 82/324 doc id 12370 rev 8 9 window watchdog (wwdg) 9.1 introduction the window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the t6 bit becomes cleared. an mcu reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. this implies that the counter must be refreshed in a limited window. 9.2 main features programmable free-running down counter conditional reset ? reset (if watchdog activated) when the downcounter value becomes less than 40h ? reset (if watchdog activated) if the downcounter is reloaded outside the window (see figure 37 ) hardware/software watchdog activation (selectable by option byte) optional reset on halt instruction (configurable by option byte) 9.3 functional description the counter value stored in the wdgcr register (bits t[6:0]), is decremented every 16384 f osc2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit downcounter (t[6:0] bits) rolls over from 40h to 3fh (t6 becomes cl eared), it initiates a re set cycle pulling low the reset pin for typically 30s. if the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. st72561-auto window watchdog (wwdg) doc id 12370 rev 8 83/324 figure 34. watchdog block diagram the application program must write in the wd gcr register at regular intervals during normal operation to prevent an mcu reset. this operation must occur only when the counter value is lower than the window register value. the value to be stored in the wdgcr register must be between ffh and c0h (see figure 35 ): enabling the watchdog: when software watchdog is selected (by option byte), the watchdog is disabled after a reset. it is enabled by setting the wdga bit in the wdgcr register, then it cannot be disabled again except by a reset. when hardware watchdog is selected (by opti on byte), the watchdog is always active and the wdga bit is not used. controlling the downcounter: this downcounter is free-running: it counts down even if the watchdog is disabled. when the watchdog is enabled, the t6 bit must be set to prevent generating an immediate reset. the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see figure 35 ). the timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the wdgcr register (see figure 36 ). the window register (wdgwr) contains the high limit of the window: to prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 3fh. figure 37 describes the window watchdog process. note: the t6 bit can be used to generate a software reset (the wdga bit is set and the t6 bit is cleared). watchdog reset on halt option: if the watchdog is activated and the watchdog reset on halt option is selected, then the halt instruction will generate a reset. reset wdga 6-bit downcounter (cnt) t6 t0 watchdog control register (wdgcr) t1 t2 t3 t4 t5 - w6 w0 watchdog window register (wdgwr) w1 w2 w3 w4 w5 comparator t6:0 > w6:0 cmp = 1 when write wdgcr wdg prescaler div 4 f osc2 12-bit mcc rtc counter msb lsb div 64 0 5 6 11 mcc/rtc tb[1:0] bits (mccsr register) window watchdog (wwdg) st72561-auto 84/324 doc id 12370 rev 8 9.4 using halt mode with the wdg if halt mode with watchdog is enabled by option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruction to refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. 9.5 how to program the watchdog timeout figure 35 shows the linear relationship between the 6-bit value to be loaded in the watchdog counter (cnt) and th e resulting timeout duration in milliseconds. this can be used for a quick calculation without taking the timing variations into account. if more precision is needed, use the formulae in figure 36 . caution: when writing to the wdgcr register, always write 1 in the t6 bit to avoid generating an immediate reset. figure 35. approximate timeout duration cnt value (hex.) watchdog timeout (ms) @ 8 mhz f osc2 3f 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114 st72561-auto window watchdog (wwdg) doc id 12370 rev 8 85/324 figure 36. exact timeout duration (t min and t max ) where : t min0 = (lsb + 128) x 64 x t osc2 t max0 = 16384 x t osc2 t osc2 = 125ns if f osc2 =8 mhz cnt = value of t[5:0] bits in the wdgcr register (6 bits) msb and lsb are values from the table below depending on the timebase selected by the tb[1:0] bits in the mccsr register to calculate the minimum watchdog timeout (t min ): if then else to calculate the maximum watchdog timeout (t max ): if then else note: in the above formulae, division results must be rounded down to the next integer value. example 1 : with 2ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mccsr reg.) selected mccsr timebase msb lsb 002ms 459 014ms 853 1 0 10ms 20 35 1 1 25ms 49 54 value of t[5:0] bits in wdgcr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t max 00 1.496 2.048 3f 128 128.552 cnt msb 4 ------------- < t min t min0 16384 cnt t osc2 + = t min t min0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = cnt msb 4 ------------- t max t max0 16384 cnt t osc2 + = t max t max0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = window watchdog (wwdg) st72561-auto 86/324 doc id 12370 rev 8 figure 37. window watchdog timing diagram 9.6 low power modes 9.7 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the wdgcr is not used. refer to the option byte description. t6 bit reset wdgwr t[5:0] cnt downcounter time refresh window refresh not allowed (step = 16384/f osc2 ) 3fh table 36. effect of low power modes on wdg mode description slow no effect on watchdog: the downcounter continues to decrement at normal speed. wait no effect on watchdog: the downcounter continues to decrement. halt oie bit in mccsr register wdghalt bit in option byte 00 no watchdog reset is generated. the mcu enters halt mode. the watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the mcu receives an external interrupt or a reset. if an interrupt is received (refer to interrupt table mapping to see interrupts which can occur in halt mode), the watchdog restarts counting after 256 or 4096 cpu clocks. if a reset is generated, the watchdog is disabled (reset state) unless hardware watchdog is selected by option byte. for application recommendations see section 9.8: using halt mode with the wdg (wdghalt option) below. 0 1 a reset is generated instead of entering halt mode. active halt 1x no reset is generated. the mcu enters active halt mode. the watchdog counter is not decremented . it stop counting. when the mcu receives an oscillator interrupt or external interrupt, the watchdog restarts counting immediately. when the mcu receives a reset the watchdog restarts counting after 256 or 4096 cpu clocks. st72561-auto window watchdog (wwdg) doc id 12370 rev 8 87/324 9.8 using halt mode with the wdg (wdghalt option) the following recommendation applies if halt mode is used when the watchdog is enabled. before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. 9.9 interrupts none. 9.10 register description 9.10.1 control register (wdgcr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit. this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watchdog option is enabled by option byte. bits 6:0 = t[6:0] 7-bit counter (msb to lsb) . these bits contain the value of the watchdog counter. it is decremented every 16384 f osc2 cycles (approx.). a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). 9.10.2 window register (wdgwr) read/ write reset value: 0111 1111 (7fh) bit 7 = reserved bits 6:0 = w[6:0] 7-bit window value these bits contain the window value to be compared to the downcounter. 7 0 wdga t6 t5 t4 t3 t2 t1 t0 7 0 - w6w5 w4w3w2w1w0 window watchdog (wwdg) st72561-auto 88/324 doc id 12370 rev 8 table 37. watchdog timer register map and reset values address (hex.) register label 7 6543210 2f wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 30 wdgwr reset value - 0 w6 1 w5 1 w4 1 w3 1 w2 1 w1 1 w0 1 st72561-auto main clock controller with real time clock mcc/rtc doc id 12370 rev 8 89/324 10 main clock controller with real time clock mcc/rtc the main clock controller consists of three different functions: a programmable cpu clock prescaler a clock-out signal to supply external devices a real time clock timer with interrupt capability each function can be used independently and simultaneously. 10.1 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal peripherals. it manages slow power saving mode (see section 7.2: slow mode for more details). the prescaler selects the f cpu main clock frequency and is controlled by three bits in the mccsr register: cp[1:0] and sms. 10.2 clock-out capability the clock-out capability is an alternate function of an i/o port pin that outputs a f osc2 clock to drive external devices. it is controlled by the mco bit in the mccsr register. 10.3 real time clock timer (rtc) the counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. four different time bases depending directly on f osc2 are available. the whole functionality is controlled by 4 bits of the mccsr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active halt mode when the halt instructio n is executed. see section 7.5: active halt mode for more details. figure 38. main clock controller (mcc/rtc) block diagram div 2, 4, 8, 16 mcc/rtc interrupt sms cp1 cp0 tb1 tb0 oie oif cpu clock mccsr rtc counter to cpu and peripherals f osc2 f cpu mco mco to watchdog timer main clock controller with real time clock mcc/rtc st72561-auto 90/324 doc id 12370 rev 8 10.4 low power modes 10.5 interrupts the mcc/rtc interrupt event generates an interrupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). note: the mcc/rtc interrupt wakes up the mcu from active halt mode, not from halt or awuf halt mode. 10.6 register description 10.6.1 mcc control/status register (mccsr) read/write reset value: 0000 0000 (00h) bit 7 = mco main clock out selection this bit enables the mco alternate function on the corresponding i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f osc2 on i/o port) bits 6:5 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software table 38. effect of low power modes on mcc/rtc mode description wait no effect on mcc/rtc peripheral. mcc/rtc interrupt cause the devi ce to exit from wait mode. active halt no effect on mcc/rtc counter (oie bi t is set), the registers are frozen. mcc/rtc interrupt cause the device to exit from active halt mode. halt and awuf halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with ?exit from halt? capability. table 39. mcc/rtc interrupt control wake-up capability interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no 1) 7 0 mco cp1 cp0 sms tb1 tb0 oie oif st72561-auto main clock controller with real time clock mcc/rtc doc id 12370 rev 8 91/324 bit 4 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc2 1: slow mode. f cpu is given by cp1, cp0 see section 7.2: slow mode and section 10: main clock controller with real time clock mcc/rtc for more details. bits 3:2 = tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software. a modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. this allows to use this time base as a real time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active halt mode. when this bit is set, calling the st7 softwa re halt instruction enters the active halt power saving mode . bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the csr register. it indicates when set that the ma in oscillator has reached the se lected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached table 40. cpu clock frequency in slow mode f cpu in slow mode cp1 cp0 f osc2 / 2 0 0 f osc2 / 4 1 f osc2 / 8 1 0 f osc2 / 16 1 table 41. time base selection counter prescaler time base tb1 tb0 f osc2 =4 mhz f osc2 =8 mhz 16000 4ms 2ms 0 0 32000 8ms 4ms 1 80000 20ms 10ms 1 0 200000 50ms 25ms 1 main clock controller with real time clock mcc/rtc st72561-auto 92/324 doc id 12370 rev 8 caution: the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. table 42. main clock controller register map and reset values address (hex.) register label 76543210 002dh sicsr reset value 0 avdie avdf lvdrf 0 00 wdgrf x 002eh mccsr reset value mco 0 cp1 0 cp0 0 sms 0 tb1 0 tb0 0 oie 0 oif 0 st72561-auto pwm auto-reload timer (art) doc id 12370 rev 8 93/324 11 pwm auto-reload timer (art) 11.1 introduction the pulse width modulated auto-reload timer on-chip peripheral consists of an 8-bit auto- reload counter with compare/ca pture capabilities and of a 7- bit prescaler clock source. these resources allow five possible operating modes: generation of up to four independent pwm signals output compare and time base interrupt up to two input capture functions external event detector up to two external interrupt sources the three first modes can be used together with a single counter frequency. the timer can be used to wake up the mcu from wait and halt modes. figure 39. pwm auto-reload timer block diagram ovf interrupt excl cc2 cc1 cc0 tce fcrl oie ovf artcsr f input pwmx port function alternate ocrx compare register programmable prescaler 8-bit counter (car register) arr register icrx register load opx polarity control oex pwmcr mux f cpu dcrx register load f counter artclk f ext articx icfx icsx iccsr load icx interrupt iciex input capture control pwm auto-reload timer (art) st72561-auto 94/324 doc id 12370 rev 8 11.2 functional description 11.2.1 counter the free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. it is possible to read or write the contents of the counter on the fly by reading or writing the counter access register (artcar). when a counter overflow occurs, the counter is automatically reloaded with the contents of the artarr register (the prescaler is not affected). 11.2.2 counter clock and prescaler the counter clock frequency is given by: f counter = f input / 2 cc[2:0] the timer counter?s input clock (f input ) feeds the 7-bit programmable prescaler, which selects one of the eight available taps of the prescaler, as defined by cc[2:0] bits in the control/status register (artcsr). thus the division factor of the prescaler can be set to 2 n (where n = 0, 1...7). this f input frequency source is selected through the excl bit of the artcsr register and can be either the f cpu or an external input frequency f ext . the clock input to the counter is enabled by the tce (timer counter enable) bit in the artcsr register. when tce is reset, the counter is stopped and the prescaler and counter contents are frozen. when tce is set, the counter runs at the rate of the selected clock source. 11.2.3 counter and pre scaler initialization after reset, the counter and th e prescaler are cleared and f input = f cpu . the counter can be initialized by: writing to the artarr register and then setting the fcrl (force counter re-load) and the tce (timer counter enable) bits in the artcsr register. writing to the artcar counter access register, in both cases the 7-bit presca ler is also cleared, whereupon counting will start from a known value. direct access to the pre scaler is not possible. 11.2.4 output compare control the timer compare function is based on four different comparisons with the counter (one for each pwmx output). each comparison is made between the counter value and an output compare register (ocrx) value. this ocrx regi ster can not be accessed directly, it is loaded from the duty cycle register (pwmdcrx) at each overflow of the counter. this double buffering method avoids glitch generation when changing the duty cycle on the fly. st72561-auto pwm auto-reload timer (art) doc id 12370 rev 8 95/324 figure 40. output compare control 11.2.5 independent pwm signal generation this mode allows up to four pulse width modulated signals to be generated on the pwmx output pins with minimum core processing over head. this function is stopped during halt mode. each pwmx output signal can be selected i ndependently using the corresponding oex bit in the pwm control register (pwmcr). when this bit is set, the corresponding i/o pin is configured as output push-pull alternate function. the pwm signals all have the same frequency which is controlled by the counter period and the artarr register value. f pwm = f counter / (256 - artarr) when a counter overflow occurs, the pwmx pin level is changed depending on the corresponding opx (output polarity) bit in the pwmcr register. when the counter reaches the value contained in one of the output compare register (ocrx) the corresponding pwmx pin level is restored. it should be noted that the reload values will also affect the value and the resolution of the duty cycle of the pwm output signal. to obtain a signal on a pwmx pin, the contents of the ocrx register must be greater than the contents of the artarr register. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (256 - artarr) note: to have the maximum resolution (1/256), the artarr register must be 0. with this maximum resolution, 0% and 100% can be obtained by changing the polarity. figure 41. pwm auto-reload timer function counter fdh feh ffh fdh feh ffh fdh feh artarr=fdh f counter ocrx pwmdcrx fdh feh fdh feh ffh pwmx duty cycle register auto-reload register pwmx output t 255 000 with oex=1 and opx=0 (artarr) (pwmdcrx) with oex=1 and opx=1 counter pwm auto-reload timer (art) st72561-auto 96/324 doc id 12370 rev 8 figure 42. pwm signal from 0% to 100% duty cycle 11.2.6 output compare and time base interrupt on overflow, the ovf flag of the artcsr register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, oie, in the artcsr register, is set. the ovf flag must be reset by the user software. this interrupt can be used as a time base in the application. 11.2.7 external clock and event detector mode using the f ext external prescaler input clock, the auto-reload timer can be used as an external clock event detector. in this mode, the artarr register is used to select the n event number of events to be counted before setting the ovf flag. n event = 256 - artarr caution: the external clock function is not available in halt mode. if halt mode is used in the application, prior to executing the halt instruction, the counter must be disabled by clearing the tce bit in the artcsr register to avoid spurious counter increments. figure 43. external event detector example (3 counts) 11.2.8 input capture function input capture mode allows the measurement of external signal pulse widths through articrx registers. counter pwmx output t with oex=1 and opx=0 fdh feh ffh fdh feh ffh fdh feh ocrx=fch ocrx=fdh ocrx=feh ocrx=ffh artarr f counter =fdh counter t fdh feh ffh fdh ovf artcsr read interrupt artarr f ext =f counter feh ffh fdh if oie = 1 interrupt if oie = 1 artcsr read =fdh st72561-auto pwm auto-reload timer (art) doc id 12370 rev 8 97/324 each input capture can generate an interrupt independently on a selected input signal transition. this event is flagged by a set of the corresponding cfx bits of the input capture control/status register (articcsr). these input capture interrupts are enabled through the ciex bits of the articcsr register. the active transition (falling or rising edge) is software progra mmable through the csx bits of the articcsr register. the read only input capture registers (articrx) are used to latch the auto-reload counter value when a transition is detected on the arti cx pin (cfx bit set in articcsr register). after fetching the interrupt vector, the cfx flags can be read to identify the interrupt source. note: after a capture detection, data transfer in the articrx register is inhibited until the next read (clearing the cfx bit). the timer interrupt remains pendi ng while the cfx flag is set when the interrupt is enabled (ciex bit set). this means, the articrx register has to be read at each capture event to clear the cfx flag. the timing resolution is given by auto-reload coun ter cycle time (1/f counter ). note: during halt mode, input capture is inhibited (the articrx is never reloaded) and only the external interrupt capability can be used. the articx signal is synchronized on cpu clock. it takes two rising edges until articrx is latched with the counter value. depending on the prescaler value and the time when the icap event occurs, the value loaded in the articrx register may be different. if the counter is clocked with the cpu clock, the value latched in articrx is always the next counter value after the event on articx occurred ( figure 44 ). if the counter clock is prescaled, it depends on the position of the articx event within the counter cycle ( figure 45 ). figure 44. input capture timing diagram, f counter = f cpu 04h counter t 01h f counter xxh 02h 03h 05h 06h 07h 05h articx pin cfx flag icap sampled interrupt f cpu icap sampled pwm auto-reload timer (art) st72561-auto 98/324 doc id 12370 rev 8 figure 45. input capture timing diagram, f counter = f cpu / 4 11.2.9 external in terrupt capability this mode allows the input capture capabilities to be used as external interrupt sources. the interrupts are generated on the edge of the articx signal. the edge sensitivity of the external interrupts is programmable (csx bit of articcsr register) and they are independently enabled through ciex bits of the articcsr register. after fetching the interrupt vector, the cfx flags can be read to identify the interrupt source. during halt mode, the external interrupts can be used to wake up the micro (if the ciex bit is set). in this case, the interrupt synchronization is done directly on the articx pin edge ( figure 46 ). figure 46. art external interrupt in halt mode 04h counter t f counter xxh 03h 04h articx pin cfx flag icrx register interrupt f cpu icap sampled 05h 04h counter t f counter xxh 03h 05h articx pin cfx flag icrx register interrupt f cpu icap sampled 05h articx pin cfx flag t interrupt st72561-auto pwm auto-reload timer (art) doc id 12370 rev 8 99/324 11.3 register description control/status register (artcsr) read/write reset value: 0000 0000 (00h) bit 7 = excl external clock this bit is set and cleared by software. it selects the input clock for the 7-bit prescaler. 0: cpu clock. 1: external clock. bit 6:4 = cc[2:0] counter clock control these bits are set and cleared by software. they determine the prescaler division ratio from f input . bit 3 = tce timer counter enable this bit is set and cleared by software. it puts the timer in the lowest power consumption mode. 0: counter stopped (prescaler and counter frozen). 1: counter running. bit 2 = fcrl force counter re-load this bit is write-only and any at tempt to read it will yield a logi cal zero. when set, it causes the contents of artarr register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. bit 1 = oie overflow interrupt enable this bit is set and cleared by software. it allo ws to enable/disable the interrupt which is generated when the ovf bit is set. 0: overflow interrupt disable. 1: overflow interrupt enable. 7 0 excl cc2 cc1 cc0 tce fcrl oie ovf table 43. counter clock control f counter with f input =8 mhz cc2 cc1 cc0 f input f input / 2 f input / 4 f input / 8 f input / 16 f input / 32 f input / 64 f input / 128 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 pwm auto-reload timer (art) st72561-auto 100/324 doc id 12370 rev 8 bit 0 = ovf overflow flag this bit is set by hardware and cleared by software reading the artcsr register. it indicates the transition of the counter from ffh to the artarr value . 0: new transition not yet reached 1: transition reached counter access register (artcar) read/write reset value: 0000 0000 (00h) bit 7:0 = ca[7:0] counter access data these bits can be set and cleared either by hardware or by software. the artcar register is used to read or write the auto-reload counter ?on the fly? (while it is counting). auto-reload register (artarr) read/write reset value: 0000 0000 (00h) bit 7:0 = ar[7:0] counter auto-reload data these bits are set and cleared by software. they are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register. this register has two pwm management functions: adjusting the pwm frequency setting the pwm duty cycle resolution 7 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 7 0 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 table 44. pwm frequency vs resolution artarr value resolution f pwm min max 0 8-bit ~0.244 khz 31.25 khz [0..127] > 7-bit ~0.244 khz 62.5 khz [128..191] > 6-bit ~0.488 khz 125 khz [192..223] > 5-bit ~0.977 khz 250 khz [224..239] > 4-bit ~1.953 khz 500 khz st72561-auto pwm auto-reload timer (art) doc id 12370 rev 8 101/324 pwm control register (pwmcr) read/write reset value: 0000 0000 (00h) bit 7:4 = oe[3:0] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels independently acting on the corresponding i/o pin. 0: pwm output disabled. 1: pwm output enabled. bit 3:0 = op[3:0] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the four pwm output signals. note: when an opx bit is modified, the pwmx output signal polarity is immediately reversed. duty cycle registers (pwmdcrx) read/write reset value: 0000 0000 (00h) bit 7:0 = dc[7:0] duty cycle data these bits are set and cleared by software. a pwmdcrx register is associated with the ocrx register of each pwm channel to determine the second edge location of the pwm signal (the first edge location is common to all channels and given by the artarr register). these pwmdcr registers allow the duty cycle to be set independently for each pwm channel. input capture control / stat us register (articcsr) read/write reset value: 0000 0000 (00h) 7 0 oe3 oe2 oe1 oe0 op3 op2 op1 op0 table 45. pwmx output level and polarity pwmx output level opx counter <= ocrx counter > ocrx 100 011 7 0 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 pwm auto-reload timer (art) st72561-auto 102/324 doc id 12370 rev 8 bit 7:6 = reserved, always read as 0. bit 5:4 = cs[2:1] capture sensitivity these bits are set and cleared by software. they determine the trigger event polarity on the corresponding input capture channel. 0: falling edge triggers capture on channel x. 1: rising edge triggers capture on channel x. bit 3:2 = cie[2:1] capture interrupt enable these bits are set and cleared by software. they enable or disable the input capture channel interrupts independently. 0: input capture channel x interrupt disabled. 1: input capture channel x interrupt enabled. bit 1:0 = cf[2:1] capture flag these bits are set by hardware and cleared by software reading the corresponding articrx register. each cfx bit indicates that an input capture x has occurred. 0: no input capture on channel x. 1: an input capture has occurred on channel x. input capture registers (articrx) read only reset value: 0000 0000 (00h) bit 7:0 = ic[7:0] input capture data these read only bits are set and cleared by hardware. an articrx register contains the 8- bit auto-reload counter value transferred by the input capture channel x event. 7 0 0 0 cs2 cs1 cie2 cie1 cf2 cf1 7 0 ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0 table 46. pwm auto-reload timer register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0031h pwmdcr3 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0032h pwmdcr2 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0033h pwmdcr1 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0034h pwmdcr0 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 st72561-auto pwm auto-reload timer (art) doc id 12370 rev 8 103/324 0035h pwmcr reset value oe3 0 oe2 0 oe1 0 oe0 0 op3 0 op2 0 op1 0 op0 0 0036h artcsr reset value excl 0 cc2 0 cc1 0 cc0 0 tce 0 fcrl 0 rie 0 ovf 0 0037h artcar reset value ca7 0 ca6 0 ca5 0 ca4 0 ca3 0 ca2 0 ca1 0 ca0 0 0038h artarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 0039h articcsr reset value 00 ce2 0 ce1 0 cs2 0 cs1 0 cf2 0 cf1 0 003ah articr1 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 003bh articr2 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 table 46. pwm auto-reload timer register map and reset values (continued) address (hex.) register label 7 6 5 4 3 2 1 0 16-bit timer st72561-auto 104/324 doc id 12370 rev 8 12 16-bit timer 12.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input signals ( input capture ) or generation of up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequencies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 12.2 main features programmable prescaler: f cpu divided by 2, 4 or 8 overflow status flag and maskable interrupt external clock input (must be at least four times slower than the cpu clock speed) with the choice of active edge 1 or 2 output compare functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt 1 or 2 input capture functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk) (a) the block diagram is shown in figure 47 . a. some timer pins may not be avai lable (not bonded) in some st7 devic es. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be ?1?. st72561-auto 16-bit timer doc id 12370 rev 8 105/324 12.3 functional description 12.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high and low. counter regi ster (cr): counter high register (chr) is the most significant byte (ms byte). counter low register (clr) is the least significant byte (ls byte). alternate counter register (acr) alternate counter high register (achr) is the m ost significant byte (ms byte). alternate counter low register (aclr) is the least significant byte (ls byte ). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit timer). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bi ts of the cr2 register, as illustrated in ta bl e 5 0 . the value in the counter register repeats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. 16-bit timer st72561-auto 106/324 doc id 12370 rev 8 figure 47. timer block diagram figure 48. 16-bit read sequence: (from counter or alternate counter register) mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requ ests have separate vectors then the last or is not present (see device interrupt vector table) (see note) csr is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte st72561-auto 16-bit timer doc id 12370 rev 8 107/324 the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they return the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, output compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interr upt remains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 12.3.2 external clock the external clock (where available) is selected if cc0 = 1 and cc1 = 1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the external clock pin extclk that will trigger the free running counter. the counter is synchronize d with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur betw een two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the cpu clock frequency. 16-bit timer st72561-auto 108/324 doc id 12370 rev 8 figure 49. counter timing diagram, internal clock divided by 2 figure 50. counter timing diagram, internal clock divided by 4 figure 51. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. 12.3.3 input capture in this section, the index, i , may be 1 or 2 because there are two input capture functions in the 16-bit timer. the two 16-bit input capture registers (ic1r and ic2r) are used to latch the value of the free running counter after a transition is detected on the icap i pin (see figure 5 ). ic i r register is a read-only register. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 ms byte ls byte icir ic i hr ic i lr st72561-auto 16-bit timer doc id 12370 rev 8 109/324 the active transition is software programmable through the iedg i bit in the control register (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). 12.3.4 procedure to use the input capture function select the following in the cr2 register: select the timer clock (cc[1:0]) (see ta bl e 5 0 ). select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). and select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). when an input capture occurs: icf i bit is set. the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 53 ). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. note: 1 after reading the icihr regist er, transfer of input capture data is inhibited and icfi will never be set until the icilr re gister is also read. 2 the icir register contains the free running counter value which corresponds to the most recent input capture. 3 the two input capture functions can be used together even if the timer also uses the two output compare functions. 4 in one pulse mode and pwm mode only input capture 2 can be used. 5 the alternate inputs (icap1 and icap2) are always directly connected to the timer. so any transitions on these pins activates the input capture function. moreover if one of the icapi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the icie bit is set. this can be avoided if the input capture function i is disabled by reading the icihr (see note 1). 6 the tof bit can be used with interrupt generation in order to measure events that go beyond the timer range (ffffh). 16-bit timer st72561-auto 110/324 doc id 12370 rev 8 figure 52. input capture block diagram figure 53. input capture timing diagram 12.3.5 output compare in this section, the index, i , may be 1 or 2 because there are two output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output compare register and the free running counter, the output compare function: assigns pins with a programmable value if the oc i e bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: the rising edge is the active edge. ms byte ls byte oc i roc i hr oc i lr st72561-auto 16-bit timer doc id 12370 rev 8 111/324 these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). 12.3.6 procedure to use the output compare function, select the following in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. select the timer clock (cc[1:0]) (see ta bl e 5 0 ). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see ta bl e 5 0 ) if the timer clock is an external clock, the formula is: where: t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (that is, clearing the ocf i bit) is done by: reading the sr regi ster while the ocf i bit is set. an access (read or write) to the oc i lr register. oc i r = t * f cpu presc oc i r = t * f ext 16-bit timer st72561-auto 112/324 doc id 12370 rev 8 the following procedure is recommended to prevent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). note: 1 after a processor write cycle to the ocihr r egister, the output compar e function is inhibited until the ocilr register is also written. 2 if the ocie bit is not set, the ocmpi pin is a general i/o port and the olvli bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3 when the timer clock is f cpu /2, ocfi and ocmpi are set while the counter value equals the ocir register value (see figure 55 ). this behavior is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocfi and ocmpi are set while the counter value equals the ocir register value (see figure 56 ). 4 the output compare functions can be used both for generating external events on the ocmpi pins even if the input capture mode is also used. 5 the value in the 16-bit oc i r register and the olvi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. 12.3.7 forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit = 1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. the folvl i bits have no effect in both one pulse mode and pwm mode. figure 54. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 st72561-auto 16-bit timer doc id 12370 rev 8 113/324 figure 55. output compare timing diagram, f timer =f cpu /2 figure 56. output compare timing diagram, f timer =f cpu /4 12.3.8 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode: 1. load the oc1r register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i ) 16-bit timer st72561-auto 114/324 doc id 12370 rev 8 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then dedicated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see ta bl e 5 0 ). then, on a valid event on the icap1 pin, the counter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specif ic timing application can be calculated using the following formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on the cc[1:0] bits, see ta b l e 5 0 ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 57 ). event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72561-auto 16-bit timer doc id 12370 rev 8 115/324 note: 1 the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3 if olvl1 = olvl2 a continuous sig nal will be seen on the ocmp1 pin. 4 the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5 when one pulse mode is used oc1r is dedicated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level olvl2 is dedicated to the one pulse mode. figure 57. one pulse mode timing example figure 58. pulse width modulation mode timing example with 2 output compare functions note: on timers with only one output compare register, a fixed frequency pwm signal can be generated using the output compare and the counter overflow to define the pulse length. 12.3.9 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r register, and so this functionality ca n not be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values written in the oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1 = 1, oc1r = 2ed0h, olvl1 = 0, olvl2 = 1 01f8 01f8 2ed3 ic1r counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 fffc fffd fffe 2ed0 2ed1 2ed2 16-bit timer st72561-auto 116/324 doc id 12370 rev 8 procedure to use pulse width modulation mode: 1. load the oc2r register with the value corresponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corresponding to the period of the pulse if (olvl1 = 0 and olvl2 = 1) using the formula in the opposite column. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc1r register. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see ta bl e 5 0 ). if olvl1 = 1 and olvl2 = 0 the length of the positive pulse is the difference between the oc2r and oc1r registers. if olvl1 = olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see ta b l e 5 0 ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72561-auto 16-bit timer doc id 12370 rev 8 117/324 f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 58 ) note: 1 after a write instruction to the ocihr register, the output co mpare function is inhibited until the ocilr register is also written. 2 the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3 the icf1 bit is set by hardware when the c ounter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4 in pwm mode the icap1 pin can not be used to perform input capture because it is disconnected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 12.4 low power modes 12.5 interrupts table 47. effect of low power modes on 16-bit timer mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting unt il halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with ?exit from halt mode? capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequently, when the mcu is woken up by an interrupt with ?exit from halt mode? capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. table 48. timer interrupt control and wake-up capability interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie ye s n o input capture 2 event icf2 output compare 1 event (not available in pwm mode) ocf1 ocie output compare 2 event (not available in pwm mode) ocf2 timer overflow event tof toie 16-bit timer st72561-auto 118/324 doc id 12370 rev 8 note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc regi ster is reset (r im instruction). 12.6 summary of timer modes 12.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. 12.7.1 control register 1 (cr1) read/ write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. table 49. timer modes modes timer resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) ye s ye s ye s ye s output compare (1 and/or 2) one pulse mode no not recommended (1) 1. see note 4 in one pulse mode no partially (2) 2. see note 5 in one pulse mode pwm mode not recommended (3) 3. see note 4 in pulse width modulation mode no 7 0 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 st72561-auto 16-bit timer doc id 12370 rev 8 119/324 bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1:forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no su ccessful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no successful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r register and ocxe is set in the cr2 regi ster. this value is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level tran sition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin whenever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 12.7.2 control register 2 (cr2) read/ write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output compare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output compare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. 7 0 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg 16-bit timer st72561-auto 120/324 doc id 12370 rev 8 bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin out puts a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r register. bit 3, 2 = cc[1:0] clock control. the timer clock mode depends on these bits: note: if the external clock pin is not available, programming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level tran sition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the counter register. 0: a falling edge trigger s the counter register. 1: a rising edge triggers the counter register. 12.7.3 control/status register (csr) read/ write (bits 7:3 read only) reset value: xxxx x0xx (xxh) bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. table 50. clock control bits timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 1 f cpu / 8 1 0 external clock (where available) 1 7 0 icf1 ocf1 tof icf2 ocf2 timd 0 0 st72561-auto 16-bit timer doc id 12370 rev 8 121/324 bit 6 = ocf1 output compare flag 1. 0: nomatch (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1:the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. bit 2 = timd timer disable. this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disabled the output functions (ocmp1 and ocmp2 pins) to reduce power consumption. access to the timer registers is still available, allowing the timer config uration to be changed, or the counter reset, while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled bits 1:0 = reserved, must be kept cleared. 12.7.4 input capture 1 hi gh register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 0 msb lsb 16-bit timer st72561-auto 122/324 doc id 12370 rev 8 12.7.5 input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 12.7.6 output compare 1 high register (oc1hr) read/ write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. 12.7.7 output compare 1 low register (oc1lr) read/ write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 12.7.8 output compare 2 high register (oc2hr) read/ write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb st72561-auto 16-bit timer doc id 12370 rev 8 123/324 12.7.9 output compare 2 low register (oc2lr) read/ write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 12.7.10 counter hi gh register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. 12.7.11 counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. 12.7.12 alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb 16-bit timer st72561-auto 124/324 doc id 12370 rev 8 12.7.13 alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. 12.7.14 input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). 12.7.15 input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 2 event). 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb table 51. 16-bit timer register map address (hex.) register name 76543210 51 cr2 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg 52 cr1 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 53 csr icf1 ocf1 tof icf2 ocf2 timd st72561-auto 16-bit timer doc id 12370 rev 8 125/324 54 ic1hr msb lsb 55 ic1lr 56 oc1hr 57 oc1lr 58 chr 59 clr 5a achr 5b aclr 5c ic2hr 5d ic2lr 5e oc2hr 5f oc2lr table 51. 16-bit timer register map (continued) address (hex.) register name 76543210 8-bit timer (tim8) st72561-auto 126/324 doc id 12370 rev 8 13 8-bit timer (tim8) 13.1 introduction the timer consists of a 8-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input signals ( input capture ) or generation of up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the clock prescaler. 13.2 main features programmable prescaler: f cpu divided by 2, 4, 8 or f osc2 divided by 8000. overflow status flag and maskable interrupt output compare functions with ? 2 dedicated 8-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt input capture functions with ? 2 dedicated 8-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 4 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2)* the block diagram is shown in figure 59 . note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signa l on a non-bonded pi n, the value will always be ?1?. 13.3 functional description 13.3.1 counter the main block of the programmable timer is a 8-bit free running upcounter and its associated 8-bit registers. these two read-only 8-bit registers contain the same value but with the difference that reading the actr register does not clear the tof bit (timer overflow flag), located in the status register, (sr). st72561-auto 8-bit timer (tim8) doc id 12370 rev 8 127/324 writing in the ctr register or actr register resets the free running counter to the fch value. both counters have a reset value of fch (this is the only value which is reloaded in the 8-bit timer). the reset value of both counters is also fch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as shown in ta b l e 5 5 . the value in the counter register repeats every 512, 1024, 2048 or 20480000 f cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or f osc2 /8000. for example, if f osc2 /8000 is selected, and f osc2 = 8 mhz, the timer frequency will be 1 ms. refer to ta b l e 5 5 . 8-bit timer (tim8) st72561-auto 128/324 doc id 12370 rev 8 figure 59. timer block diagram whatever the timer mode used (input capture, output compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffh to 00h then: the tof bit of the sr register is set. a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interr upt remains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 st7 internal bus latch1 ocmp1 icap1 f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e 0 iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 8 8 8 8 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 8 8 8 timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note) csr 1/8000 f osc2 st72561-auto 8-bit timer (tim8) doc id 12370 rev 8 129/324 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the ctr register. note: the tof bit is not cleared by accesses to actr register. the advantage of accessing the actr register rather than the ctr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). figure 60. counter timing diagram, internal clock divided by 2 figure 61. counter timing diagram, internal clock divided by 4 figure 62. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. f cpu clock fd fe ff 00 01 02 03 internal reset timer clock counter register timer overflow flag (tof) fc fd 00 01 f cpu clock internal reset timer clock counter register timer overflow flag (tof) f cpu clock internal reset timer clock counter register timer overflow flag (tof) fc fd 00 8-bit timer (tim8) st72561-auto 130/324 doc id 12370 rev 8 13.3.2 input capture in this section, the index, i , may be 1 or 2 because there are two input capture functions in the 8-bit timer. the two 8-bit input capture registers (ic1r and ic2r) are used to latch the value of the free running counter after a transition is detected on the icap i pin (see figure 63 ). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter (see ta bl e 5 5 ). procedure to use the input capture function select the following in the cr2 register: select the timer clock (cc[1:0]) (see ta bl e 5 5 ). select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). and select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). when an input capture occurs: icf i bit is set. the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 64 ). a timer interrupt is generated if the icie bit is set and the interrupt mask is cleared in the cc register. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i r register. note: 1 the icir register contains the free running counter value which corresponds to the most recent input capture. 2 the two input capture functions can be used together even if the timer also uses the two output compare functions. 3 once the icie bit is set both input capture features may trigger interrupt requests. if only one is needed in the application, the interrupt routine software needs to discard the unwanted capture interrupt. this can be done by checking the icf1 and icf2 flags and resetting them both. 4 in one pulse mode and pwm mode only input capture 2 can be used. 5 the alternate inputs (icap1 and icap2) are always directly connected to the timer. so any transitions on these pins activates the input capture function. st72561-auto 8-bit timer (tim8) doc id 12370 rev 8 131/324 moreover if one of the icapi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the icie bit is set. 6 the tof bit can be used with interrupt generation in order to measure events that go beyond the timer range (ffh). figure 63. input capture block diagram figure 64. input capture timing diagram 13.3.3 output compare in this section, the index, i , may be 1 or 2 because there are two output compare functions in the 8-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output compare register and the free running counter, the output compare function: assigns pins with a programmable value if the oc i e bit is set sets a flag in the status register generates an interrupt if enabled two 8-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. icie cc0 cc1 8-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 8-bit ic1r register ic2r register edge detect circuit1 pin pin 01 02 03 03 timer clock counter register icapi pin icapi flag icapi register note: the rising edge is the active edge . 8-bit timer (tim8) st72561-auto 132/324 doc id 12370 rev 8 these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 00h. timing resolution is one count of the free running counter: (f cpu / cc[1:0] ). procedure to use the output compare function, select the following in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. select the timer clock (cc[1:0]) (see ta bl e 5 5 ). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = output compare period (in seconds) f cpu = pll output x2 clock frequency in hertz (or f osc /2 if pll is not enabled) presc = timer prescaler factor (2, 4, 8 or 8000 depending on cc[1:0] bits, see ta bl e 5 5 ) clearing the output compare interrupt request (that is, clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i r register. note: 1 once the ocie bit is set both output compare features may trigger interrupt requests. if only one is needed in the application, the interrupt routine software needs to discard the unwanted compare interrupt. this can be done by checking the ocf1 and ocf2 flags and resetting them both. 2 if the ocie bit is not set, the ocmpi pin is a general i/o port and the olvli bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3 when the timer clock is f cpu /2, ocfi and ocmpi are set while the counter value equals the ocir register value (see figure 66 ). this behavior is the same in opm or pwm mode. oc i r = t * f cpu presc st72561-auto 8-bit timer (tim8) doc id 12370 rev 8 133/324 when the timer clock is f cpu /4, f cpu /8 or f cpu /8000, ocfi and ocmpi are set while the counter value equals the ocir register value plus 1 (see figure 67 ). 4 the output compare functions can be used both for generating external events on the ocmpi pins even if the input capture mode is also used. 5 the value in the 8-bit oc i r register and the olvi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. 13.3.4 forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit = 1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. the folvl i bits have no effect in both one pulse mode and pwm mode. figure 65. output compare block diagram figure 66. output compare timing diagram, f timer =f cpu /2 output compare 8-bit circuit oc1r register 8 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 8-bit 8-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 f cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) d3 d0 d1 d2 d3 d4 cf 8-bit timer (tim8) st72561-auto 134/324 doc id 12370 rev 8 figure 67. output compare timing diagram, f timer =f cpu /4 13.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode: 1. load the oc1r register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then dedicated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see ta bl e 5 5 ). f cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch d3 d0 d1 d2 d3 d4 cf ocmp i pin (olvl i =1) output compare flag i (ocf i ) st72561-auto 8-bit timer (tim8) doc id 12370 rev 8 135/324 then, on a valid event on the icap1 pin, the counter is initialized to fch and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specif ic timing application can be calculated using the following formula: where: t = pulse period (in seconds) f cpu = pll output x2 clock frequency in hertz (or f osc /2 if pll is not enabled) presc = timer prescaler factor (2, 4, 8 or 8000 depending on the cc[1:0] bits, see ta bl e 5 5 ) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 68 ). note: 1 the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3 if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4 the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5 when one pulse mode is used oc1r is dedic ated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level olvl2 is dedicated to the one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fch icf1 bit is set icr1 = counter oc i r value = t * f cpu presc - 5 8-bit timer (tim8) st72561-auto 136/324 doc id 12370 rev 8 figure 68. one pulse mode timing example figure 69. pulse width modu lation mode timing example 13.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r register, and so this functionality ca n not be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values written in the oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). procedure to use pulse width modulation mode: counter fc fd fe d0 d1 d2 d3 fc fd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1 = 1, oc1r = d0h, olvl1 = 0, olvl2 = 1 f8 f8 d3 ic1r counter e2 e2 fc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r = d0h, oc2r = e2, olvl1 = 0, olvl2 = 1 fc fd fe d0 d1 d2 st72561-auto 8-bit timer (tim8) doc id 12370 rev 8 137/324 1. load the oc2r register with the value corresponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corresponding to the period of the pulse if (olvl1 = 0 and olvl2 = 1) using the formula in the opposite column. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc1r register. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see ta bl e 5 5 ). if olvl1 = 1 and olvl2 = 0 the length of the positive pulse is the difference between the oc2r and oc1r registers. if olvl1 = olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = signal or pulse period (in seconds) f cpu = pll output x2 clock frequency in hertz (or f osc /2 if pll is not enabled) presc = timer prescaler factor (2, 4, 8 or 8000 depending on cc[1:0] bits, see ta bl e 5 5 ) the output compare 2 event causes the counter to be initialized to fch (see figure 69 ) note: 1 the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 2 the icf1 bit is set by hardware when the c ounter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 3 in pwm mode the icap1 pin can not be used to perform input capture because it is disconnected to the timer. the icap2 pin can be used to perform input capture (icf2 can be counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fch icf1 bit is set oc i r value = t * f cpu presc - 5 8-bit timer (tim8) st72561-auto 138/324 doc id 12370 rev 8 set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 4 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 13.4 low power modes 13.5 interrupts note: the 8-bit timer interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc regi ster is reset (r im instruction). table 52. effect of low power modes on tim8 mode description wait no effect on 8-bit timer. timer interrupts cause the device to exit from wait mode. halt 8-bit timer registers are frozen. in halt mode, the counter stops counting unt il halt mode is exited. counting resumes from the previous count when the mcu is woke n up by an interrupt with ?exit from halt mode? capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequently, when the mcu is woken up by an interrupt with ?exit from halt mode? capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. table 53. tim8 interrupt control and wake-up capability interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie ye s n o input capture 2 event icf2 output compare 1 event (not available in pwm mode) ocf1 ocie output compare 2 event (not available in pwm mode) ocf2 timer overflow event tof toie st72561-auto 8-bit timer (tim8) doc id 12370 rev 8 139/324 13.6 summary of timer modes 13.7 register description each timer is associated with three control and status registers, and with six data registers (8-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. 13.7.1 control register 1 (cr1) read/ write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. table 54. timer modes modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) ye s ye s ye s ye s output compare (1 and/or 2) one pulse mode no not recommended (1) 1. see note 4 in one pulse mode . no partially (2) 2. see note 5 in one pulse mode . pwm mode not recommended (3) 3. see note 4 in pulse width modulation mode . no 7 0 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 8-bit timer (tim8) st72561-auto 140/324 doc id 12370 rev 8 bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1:forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no su ccessful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no successful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r register and ocxe is set in the cr2 regi ster. this value is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level tran sition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin whenever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 13.7.2 control register 2 (cr2) read/ write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output compare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output compare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. 7 0 oc1e oc2e opm pwm cc1 cc0 iedg2 0 st72561-auto 8-bit timer (tim8) doc id 12370 rev 8 141/324 bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin out puts a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r register. bit 3, 2 = cc[1:0] clock control. the timer clock mode depends on these bits: bit 1 = iedg2 input edge 2. this bit determines which type of level tran sition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = reserved, must be kept at 0. 13.7.3 control/status register (csr) read only (except bit 2 r/w) reset value: 0000 0000 (00h) bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the ic1r register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read t he sr register, then read or write the oc1r register. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffh to 00h. to clear this bit, first read the sr register, then read or write the ctr register. table 55. clock control bits timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 f osc2 / 8000 (1) 1. not available in slow mode in st72f561. 11 7 0 icf1 ocf1 tof icf2 ocf2 timd 0 0 8-bit timer (tim8) st72561-auto 142/324 doc id 12370 rev 8 note: reading or writing the actr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the ic2r register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read t he sr register, then read or write the oc2r register. bit 2 = timd timer disable. this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disabled the output functions (ocmp1 and ocmp2 pins) to reduce power consumption. access to the timer registers is still available, allowing the timer config uration to be changed, or the counter reset, while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled bits 1:0 = reserved, must be kept cleared. 13.7.4 input capture 1 register (ic1r) read only reset value: undefined this is an 8-bit read only register that contai ns the counter value (transferred by the input capture 1 event). 13.7.5 output compar e 1 register (oc1r) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the value to be compared to the ctr register. 7 0 msb lsb 7 0 msb lsb st72561-auto 8-bit timer (tim8) doc id 12370 rev 8 143/324 13.7.6 output compar e 2 register (oc2r) read/ write reset value: 0000 0000 (00h) this is an 8-bit register that contains the value to be compared to the ctr register. 13.7.7 counter register (ctr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. 13.7.8 alternate counter register (actr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. 13.7.9 input capture 2 register (ic2r) read only reset value: undefined this is an 8-bit read only register that contai ns the counter value (transferred by the input capture 2 event). 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb 7 0 msb lsb 8-bit timer (tim8) st72561-auto 144/324 doc id 12370 rev 8 13.8 8-bit timer register map address (hex.) register name 76543210 3c cr2 oc1e oc2e opm pwm cc1 cc0 iedg2 0 3d cr1 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 3e csr icf1 ocf1 tof icf2 ocf2 timd 3f ic1r msb lsb 40 oc1r 41 ctr 42 actr 43 ic2r 44 oc2r st72561-auto serial peripheral interface (spi) doc id 12370 rev 8 145/324 14 serial peripheral interface (spi) 14.1 introduction the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 14.2 main features full duplex synchronous transfers (on three lines) simplex synchronous transfers (on two lines) master or slave operation 6 master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mo de fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 14.3 general description figure 70 shows the serial peripheral interface (spi) block diagram. there are three registers: spi control register (spicr) spi control/status register (spicsr) spi data register (spidr) the spi is connected to external devices through four pins: miso: master in / slave out data mosi: master out / slave in data sck: serial clock out by spi masters and input by spi slaves ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves individually and to avoid contention on the data lines. slave ss inputs can be driven by standard i/o ports on the master device. serial peripheral interface (spi) st72561-auto 146/324 doc id 12370 rev 8 figure 70. serial peripheral interface block diagram 14.3.1 functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 71 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by th e master. when the master device transmits data to a slave device via mosi pin, the sl ave device responds by sending data to the master device via the miso pin. this implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node (in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 74 ) but master and slave must be programmed with the same timing mode. spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 st72561-auto serial peripheral interface (spi) doc id 12370 rev 8 147/324 figure 71. single master/ single slave application 14.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr register (see figure 73 ). in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 72 ): if cpha = 1 (data latched on second clock edge): ss internal must be held low during the entire transmission. this im plies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by managing the ss function by software (ssm = 1 and ssi = 0 in the in the spicsr register) if cpha = 0 (data latched on first clock edge): ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. if ss is not pulled high, a write collision error will occu r when the slave writes to the shift register (see write collision error (wcol) ). figure 72. generic ss timing diagram 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software mosi/miso master ss slave ss (if cpha = 0) slave ss (if cpha = 1) byte 1 byte 2 byte 3 serial peripheral interface (spi) st72561-auto 148/324 doc id 12370 rev 8 figure 73. hardware/software slave select management 14.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). how to operate the spi in master mode to operate the spi in master mode, perform the following steps in order: 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 74 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). caution: if the spicsr register is not written first, the spicr register setting (mstr bit) may be not taken into account. the transmit sequence begins when software writes a byte in the spidr register. 14.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: the spif bit is set by hardware. an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. 1 0 ss internal ssm bit ssi bit ss external pin st72561-auto serial peripheral interface (spi) doc id 12370 rev 8 149/324 14.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the following actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 74 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in slave select management and figure 72 . if cpha = 1 ss must be held low continuously. if cpha = 0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and se t the spe bit to enable the spi i/o functions. 14.3.6 slave mo de transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its mosi pin. when data transfer is complete: the spif bit is set by hardware. an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a write or a read to the spidr register note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see overrun condition (ovr) ). 14.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 74 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge. figure 74 shows an spi transfer with the four combinations of the cpha and cpol bits. the diagram may be interpreted as a master or slave timing diagram where the sck pin, the serial peripheral interface (spi) st72561-auto 150/324 doc id 12370 rev 8 miso pin and the mosi pin are directly connected between the master and the slave device. note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. figure 74. data clock timing diagram 14.5 error flags 14.5.1 master mode fault (modf) master mode fault occurs when the master device?s ss pin is pulled low. when a master mode fault occurs: the modf bit is set and an spi interrupt request is generated if the spie bit is set. the spe bit is reset. this blocks all output from the device and disables the spi peripheral. the mstr bit is reset, thus forcing the device into slave mode. sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha = 1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha = 0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) st72561-auto serial peripheral interface (spi) doc id 12370 rev 8 151/324 clearing the modf bit is done through a software sequence: 1. a read access to the spicsr regi ster while the modf bit is set. 2. a write to the spicr register. note: to avoid any conflicts in an ap plication with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the us er to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multimaster configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multimaster conflict and allows software to handle this using an interrupt routine and either perform a reset or return to an application default state. 14.5.2 overrun condition (ovr) an overrun condition occurs when the master device has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 14.5.3 write collision error (wcol) a write collision occurs when the software trie s to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted and the softwa re write will be unsuccessful. write collisions can occur both in master and slave mode. see also slave select management . note: a "read collision" will never occu r since the received data byte is placed in a buffer in which access is always synchronous with the cpu operation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 75 ). serial peripheral interface (spi) st72561-auto 152/324 doc id 12370 rev 8 figure 75. clearing the wcol bit (write collision flag) software sequence single master and multimaster configurations there are two types of spi systems: single master system multimaster system single master system a typical single master system may be configured using a device as the master and four devices as slaves (see figure 76 ). the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line, the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are connected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with command fields. multimaster system a multimaster system may also be configured by the user. transfer of master control could be implemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multimaster system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif = 0 wcol = 0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol = 0 read spicsr read spidr note: writing to the spidr register instead of reading it does not reset the wcol bit result result st72561-auto serial peripheral interface (spi) doc id 12370 rev 8 153/324 figure 76. single master / multiple slave configuration 14.6 low power modes using the spi to wake up the device from halt mode in slave configuration, the spi is able to wake up the device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to perform an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the device from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the device enters halt mode. so, if slave selection is configured as external (see slave select management ), make sure the master drives a low level on the ss pin when the slave enters halt mode. miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave device slave device slave device slave device master device table 56. effect of low power modes on spi mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the device is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from th e spidr register when the software is running (interrupt vector fetching). if several data are received before the wake- up event, then an overrun error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. serial peripheral interface (spi) st72561-auto 154/324 doc id 12370 rev 8 14.7 interrupts note: the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 14.8 register description 14.8.1 control register (spicr) read/ write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or overrun error occurs (spif = 1, modf = 1 or ovr = 1 in the spicsr register) bit 6 = spe serial peripheral output enable this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not initially connected to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable this bit is set and cleared by software and is cl eared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to ta b l e 5 8 . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. table 57. spi interrupt control and wake-up capability interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes ye s master mode fault event modf no overrun error ovr 7 0 spie spe spr2 mstr cpol cpha spr1 spr0 st72561-auto serial peripheral interface (spi) doc id 12370 rev 8 155/324 bit 4 = mstr master mode this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity this bit is set and cleared by software. this bit determines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. bit 2 = cpha clock phase this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 58. spi master mode sck frequency 14.8.2 control/status register (spicsr) read/ write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only) this bit is set by hardware when a transfer has been completed. an interrupt is generated if serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 f cpu /16 1 f cpu /32 1 1 0 f cpu /64 0 f cpu /128 1 7 0 spif wcol ovr modf - sod ssm ssi serial peripheral interface (spi) st72561-auto 156/324 doc id 12370 rev 8 spie = 1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an external device has been completed. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. bit 6 = wcol write collision status (read only) this bit is set by hardware when a write to the spidr register is done during a transmit sequence. it is cleared by a software sequence (see figure 75 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only) this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see overrun condition (ovr) ). an interrupt is generated if spie = 1 in the spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only) this bit is set by hardware when the ss pin is pulled low in master mode (see master mode fault (modf) ). an spi interrupt can be generated if spie = 1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf = 1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe = 1) 1: spi output disabled bit 1 = ssm ss management this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see slave select management . 0: hardware management (ss managed by external pin) 1: software management (internal ss signal controlled by ssi bit. external ss pin free for general-purpose i/o) bit 0 = ssi ss internal mode this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0: slave selected 1: slave deselected st72561-auto serial peripheral interface (spi) doc id 12370 rev 8 157/324 14.8.3 data i/o register (spidr) read/ write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this regi ster will initiate transmission/ reception of another byte. note: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value located in the buffer and not the content of the shift register (see figure 70 ). 7 0 d7 d6 d5 d4 d3 d2 d1 d0 table 59. spi register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 21 spidr reset value msb xx x x x xx lsb x 22 spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 23 spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0 linsci serial communication interface (lin master/slave) st72561-auto 158/324 doc id 12370 rev 8 15 linsci serial communication interface (lin master/slave) 15.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. the lin-dedicated features support the lin (local interconnect network) protocol for both master and slave nodes. this chapter is divided into sci mode and lin mode sections. for information on general sci communications, refer to the sci mode section. for lin applications, refer to both the sci mode and lin mode sections. 15.2 sci features full duplex, asynchronous communications nrz standard format (mark/space) independently programmable transmit and receive baud rates up to 500k baud. programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags 2 receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver overrun, noise and frame error detection 6 interrupt sources ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error ? parity interrupt parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 159/324 15.3 lin features lin master ? 13-bit lin synch break generation lin slave ? automatic header handling ? automatic baud rate resynchronization based on recognition and measurement of the lin synch field (for lin slave nodes) ? automatic baud rate adjustment (at cpu frequency precision) ? 11-bit lin synch break detection capability ? lin parity check on the lin identifier field (only in reception) ? lin error management ? lin header timeout ? hot plugging support 15.4 general description the interface is externally connected to another device by two pins: tdo: transmit data output. when the transmitter is disabled, the output pin returns to its i/o port configuration. when the transmitter is enabled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as characters comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the character is complete this interface uses three types of baud rate generator: a conventional type for commonly-used baud rates an extended type with a prescaler offering a very wide range of baud rates even with non-standard osc illator frequencies a lin baud rate generator with automatic resynchronization linsci serial communication interface (lin master/slave) st72561-auto 160/324 doc id 12370 rev 8 figure 77. sci block diagram (in conventional baud rate generator mode) 15.5 sci mode - func tional description 15.5.1 conventional baud rate generator mode the block diagram of the serial control interface in conventional baud rate generator mode is shown in figure 77 . it uses four registers: 2 control registers (scicr1 and scicr2) a status register (scisr) a baud rate register (scibrr) wake up unit receiver control scisr transmit control tdre tc rdrf idle or/ nf fe pe sci control interrupt scicr1 r8 t8 scid m wake pce ps pie received data register (rdr) receive shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) scidr transmitter clock receiver clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie scicr2 lhe st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 161/324 15.5.2 extended prescaler mode two additional prescalers are available in extended prescaler mode. they are shown in figure 79 . an extended prescaler receiver register (scierpr) an extended prescaler transmitter register (scietpr) 15.5.3 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 register (see figure 78 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as a continuou s logic high level for 10 (or 11) full bit times. a break character is a character with a sufficient number of low level bits to break the normal data format followed by an extra ?1? bit to acknowledge the start bit. figure 78. word length programming 15.5.4 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle line bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle line start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break character start bit extra ?1? data character break character start bit extra ?1? data character next data character next data character linsci serial communication interface (lin master/slave) st72561-auto 162/324 doc id 12370 rev 8 character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 77 ). procedure select the m bit to define the word length. select the desired baud rate using the scibrr and the scietpr registers. set the te bit to send a preamble of 10 (m = 0) or 11 (m = 1) consecutive ones (idle line) as first transmission. access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: the tdr register is empty. the data transfer is beginning. the next data can be written in the scidr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i[|1:0] bits are cleared in the ccr register. when a transmission is taking place, a write instruction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write instruction to the scidr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a character transmission is complete (aft er the stop bit) the tc bit is set and an interrupt is generated if the tcie is set and the i[1:0] bits are cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the sh ift register with a break character. th e break character length depends on the m bit (see figure 78 ) as long as the sbk bit is set, the sci sends br eak characters to the tdo pin. after clearing this bit by software, the sci inserts a logic 1 bit at the end of the last break character to guarantee the recognition of the start bit of the next character. st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 163/324 idle line setting the te bit drives the sci to send a preamble of 10 (m = 0) or 11 (m = 1) consecutive ?1?s (idle line) before the first character. in this case, clearing and then setting the te bit during a transmission sends a preamble (idle line) after the current word. note that the preamble duration (10 or 11 consecutive ?1?s depending on the m bit) does not take into account the stop bit of the previous character. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set, that is, before writing the next byte in the scidr. 15.5.5 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least significant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) between the internal bus and the received shift register (see figure 77 ). procedure select the m bit to define the word length. select the desired baud rate using the scibrr and the scierpr registers. set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. an interrupt is generated if the rie bit is set and the i[1:0] bits are cleared in the ccr register. the error flags can be set if a frame error, noise or an overrun error has been detected during reception. clearing the rdrf bit is performed by th e following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. idle line when an idle line is detected, there is the same procedure as a data received character plus an interrupt if the ilie bit is set and the i[|1:0] bits ar e cleared in the ccr register. overrun error an overrun error occurs when a character is received when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. linsci serial communication interface (lin master/slave) st72561-auto 164/324 doc id 12370 rev 8 when an overrun error occurs: the or bit is set. the rdr content will not be lost. the shift register will be overwritten. an interrupt is generated if the rie bit is set and the i[|1:0] bits are cleared in the ccr register. the or bit is reset by an access to the scisr register followed by a scidr register read operation. noise error oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. when noise is detected in a character: the nf bit is set at the rising edge of the rdrf bit. data is transferred from the shift register to the scidr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a scisr register read operation followed by a scidr register read operation. framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise. a break is received. when the framing error is detected: the fe bit is set by hardware data is transferred from the shift register to the scidr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read operation followed by a scidr register read operation. break character when a break character is received, the sci handles it as a framing error. to differentiate a break character from a framing error, it is necessary to read the scidr. if the received value is 00h, it is a break character. otherwise it is a framing error. conventional baud rate generation the baud rates for the receiver and transmitter (rx and tx) are set independently and calculated as follows: tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 165/324 with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example 1 : if f cpu is 8 mhz (normal mode) and if pr = 13 and tr = rr = 1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is enabled. 15.5.6 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. the extended baud rate generator block diagram is described in figure 79 . the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by setting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1...255 (see scietpr register) erpr = 1...255 (see scierpr register) tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu linsci serial communication interface (lin master/slave) st72561-auto 166/324 doc id 12370 rev 8 figure 79. sci baud rate and extended prescaler block diagram 15.5.7 receiver muting and wake-up feature in multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non-addressed receivers. the non-addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupts are inhibited. a muted receiver may be woken up in one of the following ways: by idle line detection if the wake bit is reset, by address mark detection if the wake bit is set. transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 167/324 idle line detection receiver wakes up by idle line detection when the receive line has recognized an idle line. then the rwu bit is reset by hardware but the idle bit is not set. this feature is useful in a multiprocessor system when the first characters of the message determine the address and when each message ends by an idle line: as soon as the line becomes idle, every receivers is waken up and analyze the first characters of the message which indicates the addressed receiver. the receivers which are not addressed set rwu bit to enter in mute mode. consequ ently, they will not treat the ne xt characters constituting the next part of the message. at the end of the message, an idle line is sent by the transmitter: this wakes up every receivers which are ready to analyze the addressing characters of the new message. in such a system, the inter-characters space must be smaller than the idle time. address mark detection receiver wakes up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. this feature is useful in a multiprocessor s ystem when the most significant bit of each character (except for the break character) is reserved for address detection. as soon as the receivers received an address character (most significant bit = ?1?), the receivers are waken up. the receivers which are not addressed set rwu bit to enter in mute mode. consequently, they will not treat the next characters constitu ting the next part of the message. 15.5.8 parity control hardware byte parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bit in the scicr1 register. depending on the character format defined by the m bit, the possible sci character formats are as listed in ta bl e 6 0 . note: in case of wake-up by an address mark, the msb bit of the data is taken into account and not the parity bit even parity the parity bit is calculated to obtain an even nu mber of ?1s? inside the character made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. table 60. character formats (1) 1. sb = start bit, stb = stop bit, pb = parity bit m bit pce bit character format 0 0 |sb| 8 bit data |stb| 1 |sb| 7-bit data |pb|stb| 1 0 |sb| 9-bit data |stb| 1 |sb| 8-bit data |pb|stb| linsci serial communication interface (lin master/slave) st72561-auto 168/324 doc id 12370 rev 8 example 2 : data = 00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity the parity bit is calculated to obtain an odd nu mber of ?1s? inside the character made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example 3 : data = 00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode if the pce bit is set then the interface checks if the received data byte has an even number of ?1s? if even parity is selected (ps = 0) or an odd number of ?1s? if odd parity is selected (ps = 1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is generated if pcie is set in the scicr1 register. 15.6 low power modes 15.7 interrupts table 61. effect of low power modes on sci mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/ receiving until halt mode is exited. table 62. sci interrupt control and wake-up capability interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie ye s n o transmission complete tc tcie received data ready to be read rdrf rie overrun error or lin synch error detected or/lhe idle line detected idle ilie parity error pe pie lin header detection lhdf lhie st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 169/324 the sci interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 15.8 sci mode register description 15.8.1 status register (scisr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register bit 6 = tc transmission complete. this bit is set by hardware when transmission of a character containing data is complete. an interrupt is generated if tcie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a preamble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detected. this bit is set by hardware when an idle line is detected. an interrupt is generated if the ilie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdr f bit has been set itself (that is, a new idle line occurs). bit 3 = or overrun error 7 0 tdre tc rdrf idle or nf fe pe linsci serial communication interface (lin master/slave) st72561-auto 170/324 doc id 12370 rev 8 the or bit is set by hardware when the word currently being received in the shift register is ready to be transferre d into the rdr register whereas rdr f is still set. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error detected note: when this bit is set, rdr register contents will not be lost but the shift register will be overwritten. bit 2 = nf character noise flag this bit is set by hardware when noise is detect ed on a received character. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no noise 1: noise is detected note: this bit does not generate interrupt as it ap pears at the same time as the rdrf bit which itself generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a desynchronization, excessive noise or a break character is detected. it is cleared by a software sequ ence (an access to the scisr register followed by a read to the scidr register). 0: no framing error 1: framing error or break character detected note: this bit does not generate an in terrupt as it appears at the sa me time as the rdrf bit which itself generates an interrupt. if the word currently being transferred causes both a frame error and an overrun error, it will be transf erred and only the or bit will be set. bit 0 = pe parity error. this bit is set by hardware when a byte parity er ror occurs (if the pce bit is set) in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an inte rrupt is generated if pie = 1 in the scicr1 register. 0: no parity error 1: parity error detected 15.8.2 control register 1 (scicr1) read/ write reset value: x000 0000 (x0h) bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m = 1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmitted word when m = 1. 7 0 r8 t8 scid m wake pce (1) 1. this bit has a different function in lin mode, please refer to the lin mode register description. ps pie st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 171/324 bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note: the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark note: if the line bit is set, the wake bit is deactivate d and replaced by the lhdm bit. bit 2 = pce parity control enable. this bit is set and cleared by software. it selects the hardware parity control (generation and detection for byte parity, detection only for lin parity). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. th e parity will be selected after the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt c apability of the hardware parity control when a parity error is detected (pe bit set). the parity error involved can be a byte parity error (if bit pce is set and bit lpe is reset) or a lin parity error (if bit pce is set and bit lpe is set). 0: parity error interrupt disabled 1: parity error interrupt enabled 15.8.3 control register 2 (scicr2) read/ write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: in sci interrupt is generated whenever tdre = 1 in the scisr register 7 0 tie tcie rie ilie te re rwu (1) 1. this bit has a different function in lin mode, please refer to the lin mode register description. sbk (1) linsci serial communication interface (lin master/slave) st72561-auto 172/324 doc id 12370 rev 8 bit 6 = tcie transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc = 1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or = 1 or rdrf = 1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle = 1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled note: during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. when te is set there is a 1 bit-time delay before the transmission starts. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled in the scisr register 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (by setting the rwu bit) the sci must first receive a data byte, otherwise it cannot function in mute mode with wakeup by idle line detection. in address mark detection wa ke-up configuration (wake bit = 1) the rwu bit cannot be modified by software while the rdrf bit is set. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1 ? and then to ?0?, the transmitte r will send a break word at the end of the current word. 15.8.4 data register (scidr) read/ write reset value: undefined st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 173/324 contains the received or transmitted data character, depending on whether it is read from or written to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (t dr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift register (see figure 77 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 77 ). 15.8.5 baud rate register (scibrr) read/ write reset value: 0000 0000 (00h) note: when lin slave mode is disabled, the scibrr register controls the conventional baud rate generator. bits 7:6 = scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 and scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. 7 0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 7 0 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 table 63. pr prescaler pr prescaling factor scp1 scp0 1 0 0 31 4 1 0 13 1 table 64. transmitter rate divider tr dividing factor sct2 sct1 sct0 1 0 0 0 21 4 1 0 81 linsci serial communication interface (lin master/slave) st72561-auto 174/324 doc id 12370 rev 8 bits 2:0 = scr[2:0] sci receiver rate divider. these 3 bits, in conjunction with the scp[1:0] bi ts define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 15.8.6 extended receive prescaler division regi ster (scierpr) read/ write reset value: 0000 0000 (00h) bits 7:0 = erpr[7:0] 8-bit extended receive prescaler register. the extended baud rate generator is activated when a value other than 00h is stored in this register. the clock frequency from the 16 divider (see figure 79 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not active after a reset. 16 1 0 0 32 1 64 1 0 128 1 table 65. receiver rate divider rr dividing factor scr2 scr1 scr0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1 table 64. transmitter rate divider tr dividing factor sct2 sct1 sct0 7 0 erpr7 erpr6 erpr5 erpr4 erpr3 erpr2 erpr1 erpr0 st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 175/324 15.8.7 extended transm it prescaler divisi on register (scietpr) read/ write reset value: 0000 0000 (00h) bits 7:0 = etpr[7:0] 8-bit extended transmit prescaler register. the extended baud rate generator is activated when a value other than 00h is stored in this register. the clock frequency from the 16 divider (see figure 79 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not active after a reset. note: in lin slave mode, the conventional and extended baud rate generators are disabled. 15.9 lin mode - functional description. the block diagram of the serial control interface, in lin slave mode is shown in figure 81 . it uses six registers: 3 control registers: scicr1, scicr2 and scicr3 2 status registers: the scisr register an d the lhlr register mapped at the scierpr address a baud rate register: lpr mapped at the scibrr address and an associated fraction register lpfr mapped at the scietpr address the bits dedicated to lin are located in the scicr3. refer to the register descriptions in section 15.10: lin mode register description for the definitions of each bit. 15.9.1 entering lin mode to use the linsci in lin mode the following configuration must be set in scicr3 register: clear the m bit to configure 8-bit word length. set the line bit. master to enter master mode the lslv bit must be reset in this case, setting the sbk bit will send 13 low bits. then the baud rate can programmed using the scibrr, scierpr and scietpr registers. in lin master mode, the conventional and/ or extended prescaler define the baud rate (as in standard sci mode) slave set the lslv bit in the scicr3 register to enter lin slave mode. in this case, setting the sbk bit will have no effect. 7 0 etpr7 etpr6 etpr5 etpr4 etpr3 etpr2 etpr1 etpr0 linsci serial communication interface (lin master/slave) st72561-auto 176/324 doc id 12370 rev 8 in lin slave mode the lin baud rate generator is selected instead of the conventional or extended prescaler. the lin baud rate generator is common to the transmitter and the receiver. then the baud rate can be programmed using lpr and lprf registers. note: it is mandatory to set the lin configuration first before programming lpr and lprf, because the lin configuration uses a different baud rate generator from the standard one. 15.9.2 lin transmission in lin mode the same procedure as in sci mode has to be applied for a lin transmission. to transmit the lin header the proceed as follows: first set the sbk bit in the scicr2 register to start transmitting a 13-bit lin synch break reset the sbk bit load the lin synch field (0x55) in the scidr register to request synch field transmission wait until the scidr is empty (tdre bit set in the scisr register) load the lin message identifier in the scidr register to request identifier transmission. figure 80. lin characters bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit idle line start bit 8-bit word length (m bit is reset) lin synch break = 13 low bits start bit extra ?1? data character next data character bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin synch field lin synch field measurement for baud rate autosynchronization st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 177/324 figure 81. sci block diagram in lin slave mode 15.9.3 lin reception in lin mode the reception of a byte is the same as in sci mode but the linsci has features for handling the lin header automatically (identifier detection) or semiautomatically (synch break detection) depending on the lin header detection mode. the detection mode is selected by the lhdm bit in the scicr3. additionally, an automatic resynchronization feature can be activated to compensate for any clock deviation, for more details please refer to lin baud rate . lin header handling by a slave depending on the lin hea der detection method the linsci will signal the detection of a lin header after the lin synch break or after the identifier has been successfully received. wake up unit receiver control scisr transmit control tdre tc rdrf idle or/ nf fe pe sci control interrupt scicr1 r8 t8 scid m wake pce ps pie received data register (rdr) receive shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) scidr transmitter clock receiver clock f cpu / ldiv sbk rwu re te ilie rie tcie tie scicr2 lin slave baud rate auto synchronization f cpu scicr3 line lase lhie lsf lhdf extended prescaler conventional baud rate generator + /16 scibrr lpr7 lpr0 lin slave baud rate generator 0 1 unit ldum lhdm lhe lslv linsci serial communication interface (lin master/slave) st72561-auto 178/324 doc id 12370 rev 8 note: it is recommended to combine the header detection function with mute mode. putting the linsci in mute mode allows the detection of headers only and prevents the reception of any other characters. this mode can be used to wait for the next header without being interrupted by the data bytes of the current message in case this message is not relevant for the application. synch break detection (lhdm = 0) when a lin synch break is received: the rdrf bit in the scisr register is set. it indicates that the content of the shift register is transferred to the scidr register , a value of 0x00 is expected for a break. the lhdf flag in the scicr3 register indicates that a lin synch break field has been detected. an interrupt is generated if the lhie bit in the scicr3 register is set and the i[1:0] bits are cleared in the ccr register. then the lin synch field is received and measured. ? if automatic resynchronization is enabled (lase bit = 1), the lin synch field is not transferred to the shift register: there is no need to clear the rdrf bit. ? if automatic resynchronization is disabled (lase bit = 0), the lin synch field is received as a normal character and transferred to the scidr register and rdrf is set. note: in lin slave mode, the fe bit detects all frame error which does not correspond to a break. identifier detection (lhdm = 1) this case is the same as the previous one except that the lhdf and the rdrf flags are set only after the entire header has been received (this is true whether automatic resynchronization is enabled or not). this indicates that the lin identifier is available in the scidr register. note: during lin synch field measurement, the sci state machine is switched off: no characters are transferred to the data register. lin slave parity in lin slave mode (line and lslv bits are set) lin parity checking can be enabled by setting the pce bit. in this case, the parity bits of the lin identifier field are checked. the identifier character is recognized as the 3 rd received character after a break character (included): the bits involved are the two msb positions (7th and 8th bits if m = 0; 8th and 9th bits if m = 0) of the identifier character. the check is performed as specified by the lin specification: lin synch lin synch identifier parity bits field field break st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 179/324 15.9.4 lin error detection lin header error flag the lin header error flag indicates that an invalid lin header has been detected. when a lin header error occurs: the lhe flag is set an interrupt is generated if the rie bit is set and the i[1:0] bits are cleared in the ccr register. if autosynchronization is enabled (lase bit = 1), this can me an that the lin synch field is corrupted, and that the sci is in a blocked state (lsf bit is set). the only way to recover is to reset the lsf bit and then to clear the lhe bit. the lhe bit is reset by an access to the scisr register followed by a read of the scidr register. lhe/ovr error conditions when auto resynchronization is disabled (lase bit = 0), the lhe flag detects: that the received lin synch field is not equal to 55h. that an overrun occurred (as in standard sci mode) furthermore, if lhdm is set it also detects that a lin header reception timeout occurred (only if lhdm is set). when the lin auto-resynchronization is enabled (lase bit = 1), the lhe flag detects: that the deviation error on the synch field is outside the lin specif ication which allows up to +/-15.5% of period deviation bet ween the slave and master oscillators. a lin header reception timeout occurred. if t header > t header_max then the lhe flag is set. refer to figure 82 . (only if lhdm is set to 1) an overflow during the synch field measurement, which leads to an overflow of the divider registers. if lhe is set due to this error then the sci goes into a blocked state (lsf bit is set). that an overrun occurred on fields other than the synch field (as in standard sci mode) deviation error on the synch field the deviation error is checking by comparing the current baud rate (relative to the slave oscillator) with the received lin synch field (relative to the mast er oscillator). two checks are performed in parallel: the first check is based on a measurement between the first fallin g edge and the last falling edge of the synch field. let us refer to this period deviation as d: identifier field parity bits id0 start bit stop bit id1 id2 id3 id4 id5 p0 p1 identifier bits p1id1id3id4id5 = p0 id0 = id1 id2 id4 m=0 linsci serial communication interface (lin master/slave) st72561-auto 180/324 doc id 12370 rev 8 if the lhe flag is set, it means that: d > 15.625% if lhe flag is not set, it means that: d < 16.40625% if 15.625% d < 16.40625%, then the flag can be either set or reset depending on the dephasing between the signal on the rdi line and the cpu clock. the second check is based on the measurement of each bit time between both edges of the synch field: this checks that each of these bit times is large enough compared to the bit time of the current baud rate. when lhe is set due to this error then the sci goes into a blocked state (lsf bit is set). lin header time-out error when the lin identifier field detection method is used (by configuring lhdm to 1) or when lin auto-resynch ronization is enabled (lase bit = 1), the linsci automatically monitors the t header_max condition given by the lin protocol. if the entire header (up to and including the stop bit of the lin identifier field) is not received within the maximum time limit of 57 bit times then a lin header error is signalled and the lhe bit is set in the scisr register. figure 82. lin header reception timeout the time-out counter is enabled at each break detection. it is stopped in the following conditions: a lin identifier field has been received an lhe error occurred (other than a timeout error). a software reset of lsf bit (transition from high to low) occurred during the analysis of the lin synch field or if lhe bit is set due to this error during the lin synchr fiel d (if lase bit = 1) then the sci goes into a blocked state (lsf bit is set). if lhe bit is set due to this erro r during fields other than lin syn ch field or if lase bit is reset then the current received header is discarded and the sci searches for a new break field. note on lin header time-out limit according to the lin specification, the maximum length of a lin header which does not cause a timeout is equal to 1.4 * (34 + 1) = 49 t bit_master . t bit_master refers to the master baud rate. when checking this timeout, the slave node is desynchronized for the reception of the lin break and synch fields. consequently, a margin must be allowed, taking into account the lin synch lin synch identifier field field break t header st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 181/324 worst case: this occurs when the lin identifier lasts exactly 10 t bit_master periods. in this case, the lin break and synch fields last 49 - 10 = 39t bit_master periods. assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. this leads to a maximum allowed header length of: 39 x (1/0.845) t bit_master + 10t bit_master = 56.15 t bit_slave a margin is provided so that the time-out occurs when the header length is greater than 57 t bit_slave periods. if it is less than or equal to 57 t bit_slave periods, then no timeout occurs. lin header length even if no timeout occurs on the lin header, it is possible to have access to the effective lin header length (t header ) through the lhl register. this allows monitoring at software level the t frame_max condition given by the lin protocol. this feature is only av ailable when lhdm bit = 1 or when lase bit = 1. mute mode and errors in mute mode when lhdm bit = 1, if an lhe error occurs during the analysis of the lin synch field or if a lin header time-out occurs then the lhe bit is set but it does not wake up from mute mode. in this case, the current header analysis is discarded. if needed, the software has to reset lsf bit. then the sci searches for a new lin header. in mute mode, if a framing error occurs on a data (which is not a break), it is discarded and the fe bit is not set. when lhdm bit = 1, any lin header which respects the following conditions causes a wake- up from mute mode: a valid lin break field (at least 11 dominant bits followed by a recessive bit) a valid lin synch field (without deviation error) a lin identifier field without framing error. note that a lin parity error on the lin identifier field does not prevent wake-up from mute mode. no lin header time-out should occur during header reception. figure 83. lin synch field measurement lin synch break extra ?1? bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin synch field measurement = 8.t br = sm.t cpu lpr(n) lpr(n+1) lpr = t br / (16.t cpu ) = rounding (sm / 128) t cpu = cpu period t br = baud rate period t br t br = 16.lp.t cpu sm = synch measurement register (15 bits) linsci serial communication interface (lin master/slave) st72561-auto 182/324 doc id 12370 rev 8 15.9.5 lin baud rate baud rate programming is done by writing a value in the lpr prescaler or performing an automatic resynchronization as described below. automatic resynchronization to automatically adjust the baud rate based on measurement of the lin synch field: write the nominal lin prescaler value (usually depending on the nominal baud rate) in the lpfr / lpr registers. set the lase bit to enable t he auto synchron ization unit. when auto synchronization is enabled, after each lin synch break, the time duration between five falling edges on rdi is sampled on f cpu and the result of this measurement is stored in an internal 15-bit register called sm (not user accessible) (see figure 83 ). then the ldiv value (and its associated lpfr and lpr registers) are automatically updated at the end of the fifth falling edge. during lin synch field measurement, the sci state machine is stopped and no data is transferred to the data register. 15.9.6 lin slave baud rate generation in lin mode, transmission and reception are driven by the lin baud rate generator note: lin master mode uses the extended or conventional prescaler register to generate the baud rate. if line bit = 1 and lslv bit = 1 then the conventional and extended baud rate generators are disabled: the baud rate for the receiver and transmitter are both set to the same value, depending on the lin slave baud rate generator: with: ldiv is an unsigned fixed point number. the mantissa is coded on 8 bits in the lpr register and the fraction is coded on 4 bits in the lpfr register. if lase bit = 1 then ldiv is automatically updated at the end of each lin synch field. three registers are used internally to manage the auto-update of the lin divider (ldiv): ldiv_nom (nominal value written by software at lpr/lpfr addresses) ldiv_meas (results of the field synch measurement) ldiv (used to generate the local baud rate) the control and interactions of these registers is explained in figure 84 and figure 85 . it depends on the ldum bit setting (lin divider update method) note: as explained in figure 84 and figure 85 , ldiv can be updated by two concurrent actions: a transfer from ldiv_meas at the end of the lin sync field and a transfer from ldiv_nom due to a software write of lpr. if both operations occur at the same time, the transfer from ldiv_nom has priority. tx = rx = (16 * ldiv) f cpu st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 183/324 figure 84. ldiv read / write operations when ldum = 0 figure 85. ldiv read / write operations when ldum = 1 15.9.7 linsci clock tolerance linsci clock tolerance when unsynchronized when lin slaves are unsynchronized (meaning no characters have been transmitted for a relatively long time), the maximum tolerate d deviation of the linsci clock is +/-15%. if the deviation is within this range then the lin synch break is detected properly when a new reception occurs. this is made possible by the fact that masters send 13 low bits for the lin synch break, which can be interpreted as 11 low bits (13 bits -15% = 11.05) by a ?fast? slave and then considered as a lin synch break. according to the lin specification, a lin synch break is valid when its duration is greater than t sbrkts = 10. this means that the lin synch break must last at least 11 low bits. mant(7:0) ldiv frac(3:0) ldiv_nom baud rate read lpr write lpfr update at end of synch field frac(3:0) mant(7:0) ldiv_meas frac(3:0) mant(7:0) write lpr read lpfr generation lin sync field measurement write lpr mant(7:0) ldiv frac(3:0) ldiv_nom baud rate read lpr write lpfr update rdrf = 1 at end of synch field frac(3:0) mant(7:0) ldiv_meas frac(3:0) mant(7:0) write lpr read lpfr generation lin sync field measurement linsci serial communication interface (lin master/slave) st72561-auto 184/324 doc id 12370 rev 8 note: if the period desynchronization of the slave is +15% (slave too slow), the character ?00h? which represents a sequence of 9 low bits must not be interpreted as a break character (9 bits + 15% = 10.35). consequently, a valid lin synch break must last at least 11 low bits. linsci clock tolerance when synchronized when synchronization has been performed, following reception of a lin synch break, the linsci, in lin mode, has the same clock devi ation tolerance as in sci mode, which is explained below: during reception, each bit is oversampled 16 times. the mean of the 8th, 9th and 10th samples is considered as the bit value. consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation should not exceed 3.75%. 15.9.8 clock deviation causes the causes which contribute to the total deviation are: d tra : deviation due to transmitter error. note: the transmitter can be either a master or a slave (in case of a slave listening to the response of another slave). d meas : error due to the lin synch measurement performed by the receiver. d quant : error due to the baud rate quantization of the receiver. d rec : deviation of the local osc illator of the re ceiver: this deviation can occur during the reception of one complete lin message assuming that the deviation has been compensated at the beginning of the message. d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the linsci clock tolerance: d tra + d meas +d quant + d rec + d tcl < 3.75% figure 86. bit sampling in reception mode rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 185/324 15.9.9 error due to lin synch measurement the lin synch field is measured over eight bit times. this measurement is performed using a counter clocked by the cpu clock. the edge detections are performed using the cpu clock cycle. this leads to a precision of 2 cpu clock cyc les for the measurement which lasts 16*8*ldiv clock cycles. consequently, this error (d meas ) is equal to: 2 / (128*ldiv min ). ldiv min corresponds to the minimum lin prescaler content, leading to the maximum baud rate, taking into account the maximum deviation of +/-15%. 15.9.10 error due to baud rate quantization the baud rate can be adjusted in steps of 1 / (16 * ldiv). the worst case occurs when the ?real? baud rate is in the middle of the step. this leads to a quantization error (d quant ) equal to 1 / (2*16*ldiv min ). 15.9.11 impact of clock de viation on maximum baud rate the choice of the nominal baud rate (ldiv nom ) will influence both the quantization error (d quant ) and the measurement error (d meas ). the worst case occurs for ldiv min . consequently, at a given cpu frequency, the maximum possible nominal baud rate (lpr min ) should be chosen with respect to the maximum tolerated deviation given by the equation: d tra + 2 / (128 * ldiv min ) + 1 / (2 *16 * ldiv min ) + d rec + d tcl < 3.75% example: a nominal baud rate of 20kbits/s at t cpu = 125ns (8 mhz) leads to ldiv nom = 25d. ldiv min = 25 - 0.15*25 = 21.25 d meas = 2 / (128 * ldiv min ) * 100 = 0.00073% d quant = 1 / (2 * 16 * ldiv min ) * 100 = 0.0015% lin slave systems for lin slave systems (the line and lslv bits are set), receivers wake up by lin synch break or lin identifier detection (depending on the lhdm bit). hot plugging feature for lin slave nodes in lin slave mute mode (the line, lslv and rwu bits are set) it is possible to hot plug to a network during an ongoing communication flow. in this case the sci monitors the bus on the rdi line until 11 consecutive dominant bits have been detected and discards all the other bits received. linsci serial communication interface (lin master/slave) st72561-auto 186/324 doc id 12370 rev 8 15.10 lin mode register description 15.10.1 status register (scisr) read only reset value: 1100 0000 (c0h) bits 7:4 = same function as in sci mode, please refer to section 15.8: sci mode register description . bit 3 = lhe lin header error . during lin header this bit signals three error types: the lin synch field is corrupted and the sci is blocked in lin synch state (lsf bit = 1). a timeout occurred during lin header reception an overrun error was detected on one of the header field (see or bit description in section 15.8: sci mode register description ). an interrupt is generated if rie = 1 in the scicr2 register. if blocked in the lin synch state, the lsf bit must first be reset (to exit lin sync h field state and then to be able to clear lhe flag). then it is cleared by the following software sequence: an access to the scisr register followed by a read to the scidr register. 0: no lin header error 1: lin header error detected note: apart from the lin header this bit signals an overrun error as in sci mode, (see description in section 15.8: sci mode register description ) bit 2 = nf noise flag in lin master mode (line bit = 1 and lslv bit = 0) this bit has the same function as in sci mode, please refer to section 15.8: sci mode register description in lin slave mode (line bit = 1 and lslv bit = 1) this bit has no meaning. bit 1 = fe framing error. in lin slave mode, this bit is set only when a r eal framing error is detected (if the stop bit is dominant (0) and at least one of the other bits is recessive (1). it is not set when a break occurs, the lhdf bit is used instead as a break flag (if the lhdm bit = 0). it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error 1: framing error detected bit 0 = pe parity error. this bit is set by hardware when a lin parity error occurs (if the pce bit is set) in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an inte rrupt is generated if pie = 1 in the scicr1 register. 0: no lin parity error 1: lin parity error detected 7 0 tdre tc rdrf idle lhe nf fe pe st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 187/324 15.10.2 control regi ster 1 (scicr1) read/ write reset value: x000 0000 (x0h) bits 7:3 = same function as in sci mode, please refer to section 15.8: sci mode register description . bit 2 = pce parity control enable. this bit is set and cleared by software. it selects the hardware parity control for lin identifier parity check. 0: parity control disabled 1: parity control enabled when a parity error occurs, the pe bit in the scisr register is set. bit 1 = reserved bit 0 = same function as in sci mode, please refer to section 15.8: sci mode register description . 15.10.3 control regi ster 2 (scicr2) read/ write reset value: 0000 0000 (00h) bits 7:2 = same function as in sci mode, please refer to section 15.8: sci mode register description . bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: mute mode is recommended for detecting only the header and avoiding the reception of any other characters. for more details please refer to lin reception . in lin slave mode, when rdrf is set, the software can not set or clear the rwu bit. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1 ? and then to ?0?, the transmitte r will send a break word at the end of the current word. 7 0 r8 t8 scid m wake pce ps pie 7 0 tie tcie rie ilie te re rwu sbk linsci serial communication interface (lin master/slave) st72561-auto 188/324 doc id 12370 rev 8 15.10.4 control register 3 (scicr3) read/ write reset value: 0000 0000 (00h) bit 7 = ldum lin divider update method. this bit is set and cleared by software and is also cleared by hardware (when rdrf = 1). it is only used in lin slave mode. it determines how the lin divider can be updated by software. 0: ldiv is updated as soon as lpr is writt en (if no auto synchronization update occurs at the same time). 1: ldiv is updated at the next received character (when rdrf = 1) after a write to the lpr register note: if no write to lpr is performed between the setting of ldum bit and the reception of the next character, ldiv will be updated with the old value. after ldum has been set, it is possible to reset the ldum bit by software. in this case, ldiv can be modified by writing into lpr / lpfr registers. bits 6:5 = line, lslv lin mode enable bits. these bits configure the lin mode: the lin master configuration enables: the capability to send lin sy nch breaks (13 low bits) using the sbk bit in the scicr2 register. the lin slave configuration enables: the lin slave baud rate generator. the lin divider (ldiv) is then represented by the lpr and lpfr registers. the lpr and lpfr registers are read/write accessible at the address of the scibrr register and the address of the scietpr register management of lin headers. lin synch break detection (11-bit dominant). lin wake-up method (see lhdm bit) instead of the normal sci wake-up method. inhibition of break transmission capability (sbk has no effect) lin parity checking (in conjunction with the pce bit) 7 0 ldum line lslv lase lhdm lhie lhdf lsf table 66. lin mode configuration line lslv meaning 0 x lin mode disabled 1 0 lin master mode 1 lin slave mode st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 189/324 bit 4 = lase lin auto synch enable. this bit enables the auto synch unit (asu). it is set and cleared by software. it is only usable in lin slave mode. 0: auto synch unit disabled 1: auto synch unit enabled. bit 3 = lhdm lin header detection method this bit is set and cleared by software. it is only usable in lin slave mode. it enables the header detection method. in addition if the rwu bit in the scicr2 register is set, the lhdm bit selects the wake-up method (replacing the wake bit). 0: lin synch break detection method 1: lin identifier field detection method bit 2 = lhie lin header interrupt enable this bit is set and cleared by software. it is only usable in lin slave mode. 0: lin header interrupt is inhibited. 1: an sci interrupt is generated whenever lhdf = 1. bit 1 = lhdf lin header detection flag this bit is set by hardware when a lin header is detected and cleared by a software sequence (an access to the scisr register followed by a read of the scicr3 register). it is only usable in lin slave mode. 0: no lin header detected. 1: lin header detected. note: the header detection method depends on the lhdm bit: - if lhdm = 0, a header is detected as a lin synch break. - if lhdm = 1, a header is detected as a lin identifier, meaning that a lin synch break field + a lin synch field + a lin identifier field have been consecutively received. bit 0 = lsf lin synch field state this bit indicates that the lin synch field is being analyzed. it is only used in lin slave mode. in auto synchronization mode (lase bit = 1), when the sc i is in the li n synch field state it waits or counts th e falling edges on the rdi line. it is set by hardware as soon as a lin synch break is detected and cleared by hardware when the lin synch field analysis is finished (see figure 87 ). this bit can also be cleared by software to exit lin synch state and return to idle mode. 0: the current character is not the lin synch field 1: lin synch field state (lin synch field undergoing analysis) figure 87. lsf bit set and clear lin synch lin synch identifier parity bits field field break 11 dominant bits lsf bit linsci serial communication interface (lin master/slave) st72561-auto 190/324 doc id 12370 rev 8 15.10.5 lin divider registers ldiv is coded using the two registers lpr and lpfr. in lin slave mode, the lpr register is accessible at the address of the scibrr register and the lpfr register is accessible at the address of the scietpr register. 15.10.6 lin prescaler register (lpr) read/ write reset value: 0000 0000 (00h) lpr[7:0] lin prescaler (mantissa of ldiv) these 8 bits define the value of the mantissa of the lin divider (ldiv): caution: lpr and lpfr registers have different meanings when reading or writing to them. consequently bit manipulation in structions (bres or bset) should never be used to modify the lpr[7:0] bits, or the lpfr[3:0] bits. 15.10.7 lin prescaler fr action register (lpfr) read/ write reset value: 0000 0000 (00h) bits 7:4 = reserved. bits 3:0 = lpfr[3:0] fraction of ldiv these 4 bits define the fraction of the lin divider (ldiv): 7 0 lpr7 lpr6 lpr5 lpr4 lpr3 lpr2 lpr1 lpr0 table 67. ldiv mantissa lpr[7:0] rounded mantissa (ldiv) 00h sci clock disabled 01h 1 ... ... feh 254 ffh 255 7 0 0000lpfr3lpfr2lpfr1lpfr0 st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 191/324 1. when initializing ldiv, the lpfr register must be written first. then, the write to the lpr register will effectively update ldiv and so the clock generation. 2. in lin slave mode, if the lpr[7:0] register is equal to 00h, the transceiver and receiver input clocks are switched off. examples of ldiv coding: example 1 : lpr = 27d and lpfr = 12d this leads to: mantissa (ldiv) = 27d fraction (ldiv) = 12/16 = 0.75d therefore ldiv = 27.75d example 2 : ldiv = 25.62d this leads to: lpfr = rounded(16*0.62d) = rounded(9.92d) = 10d = ah lpr = mantissa (25.620d) = 25d = 1bh example 3 : ldiv = 25.99d this leads to: lpfr = rounded(16*0.99d) = rounded(15.84d) = 16d the carry must be propagated to the mantissa: lpr = mantissa (25.99) + 1 = 26d = 1ch table 68. ldiv fraction lpfr[3:0] fraction (ldiv) 0h 0 1h 1/16 ... ... eh 14/16 fh 15/16 linsci serial communication interface (lin master/slave) st72561-auto 192/324 doc id 12370 rev 8 15.10.8 lin header lengt h register (lhlr) read only reset value: 0000 0000 (00h) . note: in lin slave mode when lase = 1 or lhdm = 1, the lhlr register is accessible at the address of the scierpr register. otherwise this register is always read as 00h. bits 7:0 = lhl[7:0] lin header length. this is a read-only register, which is updated by hardware if one of the following conditions occurs: ? after each break detection, it is loaded with ?ffh?. ? if a timeout occurs on t header , it is loaded with 00h. ? after every successful lin header reception (at the same time than the setting of lhdf bit), it is loaded with a value (lhl) which gives access to the number of bit times of the lin header length (t header ). the coding of this value is explained below: lhl coding t header_max = 57 lhl(7:2) represents the mantissa of (57 - t header ) lhl(1:0) represents the fraction (57 - t header ) 7 0 lhl7 lhl6 lhl5 lhl4 lhl3 lhl2 lhl1 lhl0 table 69. lhl mantissa coding lhl[7:2] mantissa (57 - t header ) mantissa (t header ) 0h 0 57 1h 1 56 ... ... ... 39h 56 1 3ah 57 0 3bh 58 never occurs ... ... ... 3eh 62 never occurs 3fh 63 initial value st72561-auto linsci serial communication interface (lin master/slave) doc id 12370 rev 8 193/324 example of lhl coding example 1 : lhl = 33h = 001100 11b lhl(7:3) = 1100b = 12d lhl(1:0) = 11b = 3d this leads to: mantissa (57 - t header ) = 12d fraction (57 - t header ) = 3/4 = 0.75 therefore: (57 - t header ) = 12.75d and t header = 44.25d example 2 : 57 - t header = 36.21d lhl(1:0) = rounded(4*0.21d) = 1d lhl(7:2) = mantissa (36.21d) = 36d = 24h therefore lhl(7:0) = 10010001 = 91h example 3 : 57 - t header = 36.90d lhl(1:0) = rounded(4*0.90d) = 4d the carry must be propagated to the mantissa: lhl(7:2) = mantissa (36.90d) + 1 = 37d = therefore lhl(7:0) = 10110000 = a0h table 70. lhl fraction coding lhl[1:0] fraction (57 - t header ) 0h 0 1h 1/4 2h 1/2 3h 3/4 linsci serial communication interface (lin master/slave) st72561-auto 194/324 doc id 12370 rev 8 table 71. linsci1 register map and reset values addr. (hex.) register name 7 654 3 210 48 sci1sr reset value tdre 1 tc 1 rdrf 0 idle 0 or/lhe 0 nf 0 fe 0 pe 0 49 sci1dr reset value dr7 - dr6 - dr5 - dr4 - dr3 - dr2 - dr1 - dr0 - 4a sci1brr lpr (lin slave mode) reset value scp1 lpr7 0 scp0 lpr6 0 sct2 lpr5 0 sct1 lpr4 0 sct0 lpr3 0 scr2 lpr2 0 scr1 lpr1 0 scr0 lpr0 0 4b sci1cr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 4c sci1cr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 4d sci1cr3 reset value ldum 0 line 0 lslv 0 lase 0 lhdm 0 lhie 0 lhdf 0 lsf 0 4e sci1erpr lhlr (lin slave mode) reset value erpr7 lhl7 0 erpr6 lhl6 0 erpr5 lhl5 0 erpr4 lhl4 0 erpr3 lhl3 0 erpr2 lhl2 0 erpr1 lhl1 0 erpr0 lhl0 0 4f sci1etpr lpfr (lin slave mode) reset value etpr7 0 0 etpr6 0 0 etpr5 0 0 etpr4 0 0 etpr3 lpfr3 0 etpr2 lpfr2 0 etpr1 lpfr1 0 etpr0 lpfr0 0 st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 195/324 16 linsci serial communicat ion interface (lin master only) 16.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. 16.2 main features full duplex, asynchronous communications nrz standard format (mark/space) dual baud rate generator systems independently programmable transmit and receive baud rates up to 500k baud. programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags 2 receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver 4 error detection flags: ? overrun error ? noise error ?frame error ? parity error 5 interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected transmitter clock output parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode lin synch break send capability linsci serial communication interface (lin master only) st72561-auto 196/324 doc id 12370 rev 8 16.3 general description the interface is externally connected to another device by three pins (see figure 88: sci block diagram ). any sci bidirectional communicati on requires a minimum of two pins: receive data in (rdi) and transmit data out (tdo): sclk: transmitter clock output. this pin outputs the transmitter data clock for synchronous transmission (no clock pulses on start bit and stop bit, and a software option to send a clock pulse on the last data bit). this can be used to control peripherals that have shift registers (e.g. lcd drivers). the clock phase and polarity are software programmable. tdo: transmit data output. when the transmitter is disabled, the output pin returns to its i/o port configuration. when the transmitter is enabled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the frame is complete. this interface uses two types of baud rate generator: a conventional type for commonly-used baud rates, an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscilla tor frequencies. st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 197/324 figure 88. sci block diagram 16.4 functional description the block diagram of the serial control interface, is shown in figure 88 . it contains seven dedicated registers: three control registers (scicr1, scicr2 and scicr3) a status register (scisr) a baud rate register (scibrr) an extended prescaler receiver register (scierpr) an extended prescaler transmitter register (scietpr) wake up unit receiver control scisr transmit control tdre tc rdrf idle or nf fe sci control interrupt scicr1 r8 t8 m wake received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) scidr transmitter clock receiver clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie scicr2 scicr3 line -- cpol cpha lbcl clock extraction phase and polarity control sclk scid pce ps pie pe clken linsci serial communication interface (lin master only) st72561-auto 198/324 doc id 12370 rev 8 refer to the register descriptions in section 15.8: sci mode register description for the definitions of each bit. 16.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 register (see figure 89 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an extra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 89. word length programming 16.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. when the transmit enable bit (te) is set, the data in the transmit shift register is output on the tdo pin and the corresponding clock pulses are output on the sclk pin. bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra ?1? data frame break frame start bit extra ?1? data frame next data frame next data frame start bit **** ** lbcl bit controls last data clock pulse clock clock ** lbcl bit controls last data clock pulse ** ** st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 199/324 character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 89 ). procedure select the m bit to define the word length. select the desired baud rate using the scibrr and the scietpr registers. set the te bit to send an idle frame as first transmission. access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: the tdr register is empty. the data transfer is beginning. the next data can be written in the scidr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write instruction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write instruction to the scidr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shi ft register with a br eak character. the break frame length depends on the m bit (see figure 89 ). as long as the sbk bit is set, the sci send br eak frames to the tdo pi n. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. linsci serial communication interface (lin master only) st72561-auto 200/324 doc id 12370 rev 8 idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a transmission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set, that is, before writing the next byte in the scidr. lin transmission the same procedure has to be applied for lin master transmission with the following differences: clear the m bit to configure 8-bit word length. set the line bit to enter li n master mode. in this case , setting the sbk bit sends 13 low bits. 16.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least significant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) between the internal bus and the received shift register (see figure 88 ). procedure select the m bit to define the word length. select the desired baud rate using the scibrr and the scierpr registers. set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the error flags can be set if a frame error, noise or an overrun error has been detected during reception. clearing the rdrf bit is performed by th e following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci handles it as a framing error. st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 201/324 idle character when an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is received when rdrf has not been reset. data cannot be transferred from the shift register to the rdr register until the rdrf bit is cleared. when a overrun error occurs: the or bit is set. the rdr content is not lost. the shift register is overwritten. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the scisr register followed by a scidr register read operation. noise error oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. when noise is detected in a frame: the nf is set at the rising edge of the rdrf bit. data is transferred from the shift register to the scidr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a scisr register read operation followed by a scidr register read operation. framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise. a break is received. when the framing error is detected: the fe bit is set by hardware data is transferred from the shift register to the scidr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read operation followed by a scidr register read operation. linsci serial communication interface (lin master only) st72561-auto 202/324 doc id 12370 rev 8 figure 90. sci baud rate and extended prescaler block diagram 16.4.4 conventional b aud rate generation the baud rates for the receiver and transmitter (rx and tx) are set independently and calculated as follows : with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64, 128 (see sct[2:0] bits) transmitter receiver scietpr scierpr extended presca ler receiver rate control extended pres caler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitte r prescaler register tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 203/324 rr = 1, 2, 4, 8, 16, 32, 64, 128 (see scr[2:0] bits) all these bits are in the scibrr register. example 1 : if f cpu is 8 mhz (normal mode) and if pr = 13 and tr = rr = 1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is enabled. 16.4.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. the extended baud rate generator block diagram is described in the figure 90 . the output clock rate sent to the transmitter or to the receiver is the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by setting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1...255 (see scietpr register) erpr = 1...255 (see scierpr register) 16.4.6 receiver muting and wake-up feature in multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits cannot be set. all the receive interrupts are inhibited. a muted receiver may be awakened by one of the following two ways: by idle line detection if the wake bit is reset, by address mark detection if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognized an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu linsci serial communication interface (lin master only) st72561-auto 204/324 doc id 12370 rev 8 receiver wakes-up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. 16.4.7 parity control parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in ta bl e 7 2 . note: in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit. even parity the parity bit is calculated to obtain an even number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example 1 : data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (ps bit = 0). odd parity the parity bit is calculated to obtain an odd number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (ps bit = 1). transmission mode if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode if the pce bit is set then the interface checks if the received data byte has an even number of ?1s? if even parity is selected (ps = 0) or an odd number of ?1s? if odd parity is selected (ps = 1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is generated if pie is set in the scicr1 register. table 72. frame formats m bit pce bit sci frame (1) 1. sb: start bit stb: stop bit pb: parity bit 0 0 | sb | 8 bit data | stb | 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 | sb | 8-bit data pb | stb | st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 205/324 16.5 low power modes 16.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 16.7 sci synchronous transmission the sci transmitter allows the user to control a one way synchronous serial transmission. the sclk pin is the output of the sci transmit ter clock. no clock pulses are sent to the sclk pin during start bit and stop bit. dependi ng on the state of the lbcl bit in the scicr3 register, clock pulses are or are not be generated during the last valid data bit (address mark). the cpol bit in the scicr3 register allows the user to select the clock polarity, and the cpha bit in the scicr3 register allows the user to select the phase of the external clock (see figure 91 , figure 92 and figure 93 ). during idle, preamble and send break, the external sclk clock is not activated. these options allow the user to serially control peripherals which consist of shift registers, without losing any functions of the sci transmitte r which can still talk to other sci receivers. these options do not affect the sci receiver which is independent from the transmitter. table 73. effect of low power modes on sci mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting /receiving until halt mode is exited. table 74. sci interrupt control and wake-up capability interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie ye s n o transmission complete tc tcie received data ready to be read rdrf rie overrun error detected or idle line detected idle ilie parity error pe pie linsci serial communication interface (lin master only) st72561-auto 206/324 doc id 12370 rev 8 note: the sclk pin works in conjunction with the tdo pin. when the sci transmitter is disabled (te and re = 0), the sclk and tdo pins go into high impedance state. the lbcl, cpol and cpha bits have to be selected before enabling the transmitter to ensure that the clock pulses function correctl y. these bits should not be changed while the transmitter is enabled. figure 91. sci example of synchronous and asynchronous transmission figure 92. sci data clock timing diagram (m = 0) asynchronous synchronous (e.g. modem) (e.g. shift register) rdi tdo sclk output port enable clock data in data in data out sci m = 0 (8 data bits) clock (cpol=0, cpha=1) clock (cpol=1, cpha=0) clock (cpol=1, cpha=1) start lsb msb stop * lbcl bit controls last data clock pulse start idle or preceding transmission data stop clock (cpol=0, cpha=0) 01 234 56 7 * * * * idle or next transmission st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 207/324 figure 93. sci data clock timing diagram (m = 1) 16.8 register description 16.8.1 status register (scisr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note: data is not be transferred to the shift register until the tdre bit is cleared. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data is complete. an interrupt is generated if tcie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a preamble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a idle or next m = 1 (9 data bits) clock (cpol=0, cpha=1) clock (cpol=1, cpha=0) clock (cpol=1, cpha=1) start lsb msb stop * lbcl bit controls last data clock pulse start idle or preceding transmission data stop clock (cpol=0, cpha=0) 01 234 56 7 * * * * 8 transmission 7 0 tdre tc rdrf idle or nf fe pe linsci serial communication interface (lin master only) st72561-auto 208/324 doc id 12370 rev 8 software sequence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when an idle line is detected. an interrupt is generated if the ilie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit is not be set again until the rdrf bit has been set itself (that is, a new idle line occurs). bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf = 1. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set, the rdr register content is not lost but the shift register is overwritten. bit 2 = nf noise flag. this bit is set by hardware w hen noise is detected on a received frame. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap pears at the same time as the rdrf bit which itself generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. it is cleared by a software sequ ence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate an in terrupt as it appears at the sa me time as the rdrf bit which itself generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it is transferred and only the or bit is set. bit 0 = pe parity error. this bit is set by hardware when a parity error occurs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an interrupt is generated if pie = 1 in the scicr1 register. 0: no parity error 1: parity error st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 209/324 16.8.2 control register 1 (scicr1) read/ write reset value: x000 0000 (x0h) bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m = 1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmitted word when m = 1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note: the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bit 2 = pce parity control enable. this bit selects the hardware parity control (generation and detection). when the parity control is enabled, the computed parity is inserted at the msb position (9th bit if m = 1; 8th bit if m = 0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmission). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity is selected after the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt c apability of the hardware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled 7 0 r8 t8 scid m wake pce ps pie linsci serial communication interface (lin master only) st72561-auto 210/324 doc id 12370 rev 8 16.8.3 control register 2 (scicr2) read/ write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre = 1 in the scisr register bit 6 = tcie transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc = 1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or = 1 or rdrf = 1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle = 1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled note: during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. when te is set there is a 1 bit-time delay before the transmission starts. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (by setting the rwu bit) the sci must first receive a data byte, otherwise it cannot function in mute mode with wakeup by idle line detection. in address mark detection wake-up configuration (wake bit = 1) the rwu bit cannot be modified by software while the rdrf bit is set. 7 0 tie tcie rie ilie te re rwu sbk st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 211/324 bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter sends a break word at the end of the current word. 16.8.4 control register 3 (scicr3) read/ write reset value: 0000 0000 (00h) bit 7 = reserved, must be kept cleared. bit 6 = line lin mode enable. this bit is set and cleared by software. 0: lin mode disabled 1: lin master mode enabled the lin master mode enables th e capability to send lin sync h breaks (13 low bits) using the sbk bit in the scicr2 register. in transmission, the lin synch break low phase duration is shown as below: bits 5:4 = reserved, forced by hardware to 0. these bits are not used. bit 3 = clken clock enable. this bit allows the user to enable the sclk pin. 0: slk pin disabled 1: slk pin enabled bit 2 = cpol clock polarity. this bit allows the user to select the polarity of the clock output on the sclk pin. it works in conjunction with the cpha bit to produce the desired clock/data relationship (see figure 92 and figure 93 ). 0: steady low value on sclk pin outside transmission window. 1: steady high value on sclk pin outside transmission window. 7 0 - line - - clken cpol cpha lbcl table 75. lin sync break duration line m number of low bits sent during a lin synch break 0 010 111 1 013 114 linsci serial communication interface (lin master only) st72561-auto 212/324 doc id 12370 rev 8 bit 1 = cpha clock phase . this bit allows the user to select the phase of the clock output on the sclk pin. it works in conjunction with the cpol bit to produce the desired clock/data relationship (see figure 92 and figure 93 ) 0: sclk clock line activated in middle of data bit. 1: sclk clock line activated at beginning of data bit. bit 0 = lbcl last bit clock pulse. this bit allows the user to select whether the clock pulse associated with the last data bit transmitted (msb) has to be output on the sclk pin. 0: the clock pulse of the last data bit is not output to the sclk pin. 1: the clock pulse of the last data bit is output to the sclk pin. note: the last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by the m bit in the scicr1 register. note: these 3 bits ( cpol , cpha , lbcl ) should not be wr itten while the transmitter is enabled. 16.8.5 data register (scidr) read/ write reset value: undefined contains the received or transmitted data character, depending on whether it is read from or written to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (t dr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift register (see figure 88 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 88 ). table 76. sci clock on sclk pin data format m bit lbcl bit number of clock pulses on sclk 8 bit 0 07 18 9 bit 1 08 19 7 0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 213/324 16.8.6 baud rate register (scibrr) read/ write reset value: 0000 0000 (00h) bits 7:6 = scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 and scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. note: this tr factor is used only when the etpr fine tuning factor is equal to 00h; otherwise, tr is replaced by the (tr*etpr) dividing factor. bits 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 and scp0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 7 0 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 table 77. pr prescaler pr prescaling factor scp1 scp0 1 0 0 31 4 1 0 13 1 table 78. transmitter rate divider tr dividing factor sct2 sct1 sct0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1 linsci serial communication interface (lin master only) st72561-auto 214/324 doc id 12370 rev 8 note: this rr factor is used only when the erpr fine tuning factor is equal to 00h; otherwise, rr is replaced by the (rr*erpr) dividing factor. 16.8.7 extended receive prescaler division regi ster (scierpr) read/ write reset value: 0000 0000 (00h) bits 7:0 = erpr[7:0] 8-bit extended receive prescaler register. the extended baud rate generator is activated when a value other than 00h is stored in this register. the clock frequency from the 16 divider (see figure 90 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not active after a reset. 16.8.8 extended transm it prescaler divisi on register (scietpr) read/ write reset value: 0000 0000 (00h) bits 7:0 = etpr[7:0] 8-bit extended transmit prescaler register. the extended baud rate generator is activated when a value other than 00h is stored in this register. the clock frequency from the 16 divider (see figure 90 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not active after a reset. table 79. receiver rate divider rr dividing factor scr2 scr1 scr0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1 7 0 erpr7 erpr6 erpr5 erpr4 erpr3 erpr2 erpr1 erpr0 7 0 etpr7 etpr6 etpr5 etpr4 etpr3 etpr2 etpr1 etpr0 st72561-auto linsci serial communication interface (lin master only) doc id 12370 rev 8 215/324 table 80. baud rate selection symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr) = 128, pr = 13 tr (or rr) = 32, pr = 13 tr (or rr) = 16, pr =13 tr (or rr) = 8, pr = 13 tr (or rr) = 4, pr = 13 tr (or rr) = 16, pr = 3 tr (or rr) = 2, pr = 13 tr (or rr) = 1, pr =13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erpr) = 35, tr (or rr) = 1, pr = 1 14400 ~14285.71 table 81. linsci2 register map and reset values address (hex.) register name 76543210 60 sci2sr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 61 sci2dr reset value dr7 - dr6 - dr5 - dr4 - dr3 - dr2 - dr1 - dr0 - 62 sci2brr reset value scp1 0 scp0 0 sct2 0 sct1 0 sct0 0 scr2 0 scr1 0 scr0 0 63 sci2cr1 reset value r8 - t8 - scid - m - wake - pce ps pie 64 sci2cr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 65 sci2cr3 reset value 0 line 0 - 0 - 0 clken 0 cpol 0 cpha 0 lbcl 0 66 sci2erpr reset value erpr7 0 erpr6 0 erpr5 0 erpr4 0 erpr3 0 erpr2 0 erpr1 0 erpr0 0 67 sci2etpr reset value etpr7 0 etpr6 0 etpr5 0 etpr4 0 etpr3 0 etpr2 0 etpr1 0 etpr0 0 becan controller (becan) st72561-auto 216/324 doc id 12370 rev 8 17 becan controller (becan) the becan controller (basic enhanced can), interfaces the can network and supports the can protocol version 2.0a and b. it has been designed to manage high number of incoming messages efficiently with a minimum cpu load. it also meets the priority requirements for transmit messages. 17.1 main features supports can protocol version 2.0 a, b active bit rates up to 1mbit/s transmission 2 transmit mailboxes configurable transmit priority reception 1 receive fifo with three stages 6 scalable filter banks identifier list feature configurable fifo overrun management maskable interrupts software-efficient mailbox mapping at a unique address space 17.2 general description in today?s can applications, the number of nodes in a network is increasing and often several networks are linked together via gateways. typically the number of messages in the system (and thus to be handled by each node) has significantly increased. in addition to the application messages, network management and diagnostic messages have been introduced. an enhanced filtering mechanism is required to handle each type of message. furthermore, application tasks require more cpu time, therefore real-time constraints caused by message reception have to be reduced. a receive fifo scheme allows the cpu to be dedicated to application tasks for a long time period without losing messages. the standard hlp (higher layer protocol) based on standard can drivers requires an efficient interface to the can controller. all mailboxes and registers are organized in 16-byte pages mapped at the same address and selected via a page select register. st72561-auto becan controller (becan) doc id 12370 rev 8 217/324 figure 94. can network topology can 2.0b active core the becan module handles the transmission and the reception of can messages fully autonomously. standard identifiers (11-bit) and extended identifiers (29-bit) are fully supported by hardware. control, status and configuration registers the application uses these registers to: configure can parameters, e.g.baud rate request transmissions handle receptions manage interrupts get diagnostic information tx mailboxes two transmit mailboxes are provided to the software for setting up messages. the transmission scheduler decides which mailbox has to be transmitted first. acceptance filters the becan provides six scalable/configurable identifier filter banks for selecting the incoming messages the software needs and discarding the others. receive fifo the receive fifo is used by the can controller to store the incoming messages. three complete messages can be stored in the fifo. the software always accesses the next available message at the same address. the fifo is managed completely by hardware. can node 1 can node 2 can node n can can high low can can rx tx can transceiver can controller st9 mcu can bus application becan controller (becan) st72561-auto 218/324 doc id 12370 rev 8 figure 95. can block diagram figure 96. becan operating modes 17.3 operating modes the becan has three main operating modes: initialization, normal and sleep. after a hardware reset, becan is in sleep mode to reduce power consumption. the software requests becan to enter initia lization or sleep mode by setting the inrq or sleep bits in the cmcr register. once the mode has been entered, becan confirms it by setting the inak or slak bits in the cmsr register. when neither inak nor slak are set, becan is in 1 4 5 can 2.0b active core mailbox 0 transmission filter 1 2 3 mailbox 1 mailbox 0 1 2 receive fifo acceptance filters tx mailboxes master control scheduler master status transmit status transmit prio receive fifo error status error int. enable tx error counter rx error counter diagnostic bit timing filter master filter config. page select interrupt enable 0 control/status/configuration sleep sync initialization normal s l e e p s l e e p * i n r q i n r q i n r q reset slak= 1 inak = 0 slak= x inak = x slak= 0 inak = 1 s l e e p s l e e p slak= 0 inak = 0 inrq st72561-auto becan controller (becan) doc id 12370 rev 8 219/324 normal mode. before entering normal mode becan always has to synchronize on the can bus. to synchronize, becan waits until the can bus is idle, this means 11 consecutive recessive bits have been monitored on canrx. initialization mode the software initializat ion can be done while the hardware is in initialization mode. to enter this mode the software sets the inrq bit in the cmcr register and waits until the hardware has confirmed the request by setting the inak bit in the cmsr register. to leave initialization mode, the software clears the inqr bit. becan has left initialization mode once the inak bit has been cleared by hardware. while in initialization mode, all message transfers to and from the can bus are stopped and the status of the can bus output cantx is recessive (high). entering initialization mode does not change any of the configuration registers. to initialize the can controller, software has to set up the bit timing registers and the filter banks. if a filter bank is not used, it is recommended to leave it non active (leave the corresponding fact bit cleared). normal mode once the initialization has been done, the software must request the hardware to enter normal mode, to synchronize on the can bus and start reception and transmission. entering normal mode is done by clearing the inrq bit in the cmcr register and waiting until the hardware has confirmed the request by clearing the inak bit in the cmsr register. afterwards, the becan synchronizes with the data transfer on the can bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits ( bus idle) before it can take part in bus activities and start message transfer. the initialization of the filter values is independent from initialization mode but must be done while the filter bank is not active (corresponding factx bit cleared). the filter bank scale and mode configuration must be co nfigured in initialization mode. low power mode (sleep) to reduce power consumption, becan has a low power mode called sleep mode. this mode is entered on software re quest by setting the sleep bit in the cmcr register. in this mode, the becan clock is st opped. consequently, software can still access the becan registers and mailboxes but the becan will not update the status bits. example 1 : if software requests entry to initialization mode by setting the inrq bit while becan is in sleep mode, it will not be acknowledged by the hardware, inak stays cleared. becan can be woken up (exit sleep mode) eith er by software clearing the sleep bit or on detection of can bus activity. on can bus activity detection, hardware automatically performs the wake-up sequence by clearing the sleep bit if the awum bit in the cmcr register is set. if the awum bit is cleared, software has to clear the sleep bit when a wake-up in terrupt occurs, in order to exit from sleep mode. note: if the wake-up interr upt is enabled (wkuie bit set in ci er register) a wake-up interrupt will be generated on detection of can bus activity, even if the becan automatically performs the wake-up sequence. becan controller (becan) st72561-auto 220/324 doc id 12370 rev 8 after the sleep bit has been cleared, sleep mode is exited once becan has synchronized with the can bus, refer to figure 96 . the sleep mode is exited once the slak bit has been cleared by hardware. test mode test mode can be selected by the silm and lbkm bits in the cdgr register. these bits must be configured while becan is in initialization mode. once test mode has been selected, becan is started in normal mode. silent mode the becan can be put in silent mode by setting the silm bit in the cdgr register. in silent mode, the becan is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the can bus and it cannot start a transmission. if the becan has to send a dominant bit (ack bit, overload flag, active error flag), the bit is rerouted internally so that the can core monitors this dominant bit, although the can bus may remain in recessive state. silent mode can be used to analyze the traffic on a can bus without affecting it by the transmission of dominant bits (acknowledge bits, error frames). figure 97. becan in silent mode loop back mode the becan can be set in loop back mode by setting the lbkm bit in the cdgr register. in loop back mode, the becan treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) in the fifo. figure 98. becan in loop back mode this mode is provided for self-test functions. to be independent of external events, the can core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a data becan cantx canrx tx rx =1 becan cantx canrx tx rx st72561-auto becan controller (becan) doc id 12370 rev 8 221/324 / remote frame) in loop back mode. in this mode, the becan performs an internal feedback from its tx output to its rx input. the actual value of the canrx input pin is disregarded by the becan. the transmitted messages can be monitored on the cantx pin. loop back combined with silent mode it is also possible to combine loop back mode and silent mode by setting the lbkm and silm bits in the cdgr register. this mode can be used for a ?hot selftest?, meaning the becan can be tested like in loop back mode but without affecting a running can system connected to the cantx and canrx pins. in this mode, the canrx pin is disconnected from the becan and the cantx pin is held recessive. figure 99. becan in combined mode 17.4 functional description 17.4.1 transmission handling in order to transmit a message, the application must select one empty transmit mailbox, set up the identifier, the data length code (dlc) and the data before requesting the transmission by setting the corresponding txrq bit in the mcsr register. once the mailbox has left empty state, the software no longer has write access to the mailbox registers. immediately after the txrq bit has been set, the mailbox enters pending state and waits to become the highest priority mailbox, see transmit priority . as soon as the mailbox has the highest priority it will be scheduled for transmissi on. the transmission of the message of the scheduled mailbox will start (enter transmit state) when the can bus becomes idle. once the mailbox has been successf ully transmitted, it will beco me empty again. the hardware indicates a successful transmission by setting the rqcp and txok bits in the mcsr and ctsr registers. if the transmission fails, the cause is indicated by the alst bit in the mcsr register in case of an arbitration lost, and/or the terr bit, in case of transmission error detection. transmit priority by identifier: when more than one transmit mailbox is pending, the transmission order is given by the identifier of the message stored in the mailbox. the message with the lowest identifier value has the highest priority according to the arbitration of the can protocol. if the identifier values are equal, the lower mailbox number will be scheduled first. becan cantx canrx tx rx =1 becan controller (becan) st72561-auto 222/324 doc id 12370 rev 8 by transmit request order: the transmit mailboxes can be configured as a transmit fifo by setting the txfp bit in the cmcr register. in this mode the priority order is given by the transmit request order. this mode is very useful for segmented transmission. abort a transmission request can be aborted by the user setting the abrq bit in the mcsr register. in pending or scheduled state, the mailbox is aborted immediately. an abort request while the mailbox is in transmit st ate can have two results. if the mailbox is transmitted successfully the mailbox becomes empty with the txok bit set in the mcsr and ctsr registers. if the transmission fails, the mailbox becomes scheduled, the transmission is aborted and be comes empty with txok cleared. in all cases the mailbox will become empty again at least at the end of the current transmission. non-automatic retransmission mode to configure the hardware in this mode the nart bit in the cmcr register must be set. in this mode, each transmission is started only once. if the first attempt fails, due to an arbitration loss or an error, the hardware will not automatically restart the message transmission. at the end of the first transmission attempt, the hardware considers the request as completed and sets the rqcp bit in the mcsr register. the result of the transmission is indicated in the mcsr register by the txok, alst and terr bits. figure 100. transmit mailbox states 17.4.2 reception handling for the reception of can messages, three mailboxes organized as a fifo are provided. in order to save cpu load, simplify the software and guarantee data consistency, the fifo is empty txrq=1 rqcp=x txok=x pending rqcp=0 txok=0 scheduled rqcp=0 txok=0 mailbox has transmit rqcp=0 txok=0 can bus = idle transmit failed * nart transmit succeeded mailbox does not empty rqcp=1 txok=0 highest priority have highest priority empty rqcp=1 txok=1 abrq=1 abrq=1 transmit failed * nart tme = 1 tme = 0 tme = 0 tme = 0 tme = 1 tme = 1 st72561-auto becan controller (becan) doc id 12370 rev 8 223/324 managed completely by hardware. the application accesses the messages stored in the fifo through the fifo output mailbox. valid message a received message is considered as valid when it has been received correctly according to the can protocol (no error until the last but one bit of the eof field) and it passed through the identifier filtering successfully, see identifier filtering . figure 101. receive fifo states fifo management starting from the empty state, the first valid message received is stored in the fifo which becomes pending_1. the hardware signals the event setting the fmp[1:0] bits in the crfr register to the value 01b. the message is available in the fifo output mailbox. the software reads out the mailbox content and releases it by setting the rfom bit in the crfr register. the fifo becomes empty again. if a new valid message has been received in the meantime, the fifo stays in pending_1 state and the new message is available in the output mailbox. if the application does not rele ase the mailbox, the next valid message will be stored in the fifo which enters pending_2 state (fmp[1:0] = 10b). the storage process is repeated for the next valid message putting the fifo into pending_3 state (fmp[1:0] = 11b). at this point, empty valid message fmp=0x00 fovr=0 pending_1 fmp=0x01 fovr=0 received pending_2 fmp=0x10 fovr=0 pending_3 fmp=0x11 fovr=0 valid message received release overrun fmp=0x11 fovr=1 mailbox release mailbox valid message received valid message received release mailbox release mailbox valid message received rfom=1 rfom=1 rfom=1 becan controller (becan) st72561-auto 224/324 doc id 12370 rev 8 the software must release the output mailbox by setting the rfom bit, so that a mailbox is free to store the next valid message. otherwis e the next valid message received will cause a loss of message. refer also to message storage . overrun once the fifo is in pending_3 state (that is, the three mailboxes are full) the next valid message reception will lead to an overrun an d a message will be lost. the hardware signals the overrun condition by setting the fovr bit in the crfr register. which message is lost depends on the configuration of the fifo: if the fifo lock function is disabled (rflm bit in the cmcr register cleared) the last message stored in the fifo will be overwri tten by the new incoming message. in this case the latest messages will be alwa ys available to the application. if the fifo lock function is enabled (rflm bit in the cmcr register set) the most recent message will be discarde d and the software will have the three oldest messages in the fifo available. reception related interrupts on the storage of the first message in the fifo - fmp[1:0] bits change from 00b to 01b - an interrupt is generated if the fmpie bit in the cier register is set. when the fifo becomes full (that is, a third message is stored) the full bit in the crfr register is set and an interrupt is generated if the ffie bit in the cier register is set. on overrun condition, the fovr bit is set and an interrupt is generated if the fovie bit in the cier register is set. 17.4.3 identifier filtering in the can protocol the identifier of a message is not associated with the address of a node but related to the content of the message. consequently a transmitter broadcasts its message to all receivers. on message reception a receiver node decides - depending on the identifier value - whether the software needs the message or not. if the message is needed, it is copied into the ram. if not, the message must be discarded without intervention by the software. to fulfil this requiremen t, the becan controller provides six configurable and scalable filter banks (0-5) in order to receive only the messages the software needs. this hardware filtering saves cpu resources which would be otherwise needed to perform filtering by software. each filter bank consists of eight 8-bit registers, cfxr[0:7]. scalable width to optimize and adapt the filters to the application needs, each filter bank can be scaled independently. depending on the filter scale a filter bank provides: one 32-bit filter for the stdid[10:0], ide, extid[17:0] and rtr bits. two 16-bit filters for the stdid[10:0], rtr and ide bits. four 8-bit filters for the stdid[10:3] bits. th e other bits are considered as ?don?t care?. one 16-bit filter and two 8-bit filters for filtering the same set of bits as the 16 and 8-bit filters described above. refer to figure 102 . st72561-auto becan controller (becan) doc id 12370 rev 8 225/324 furthermore, the filters can be configured in mask mode or in identifier list mode. mask mode in mask mode the identifier registers are associat ed with mask registers specifying which bits of the identifier are handled as ?must match? or as ?don?t care?. identifier list mode in identifier list mode, the mask registers are used as identifier registers. thus instead of defining an identifier and a mask, two identifiers are specified, doubling the number of single identifiers. all bits of the incoming identifier must match the bits specified in the filter registers. figure 102. filter bank scale configuration - register organization filter bank scale and mode configuration the filter banks are configured by means of the corresponding cfcrx register. to configure a filter bank this must be deactivated by clearing the fact bit in the cfcr register. the filter scale is configured by means of the fsc[1:0] bits in the corresponding cfcr register, refer one 32-bit filter two 16-bit filters one 16-bit / two 8-bit filters four 8-bit filters cfxr0 cfxr4 cfxr1 cfxr5 cfxr2 cfxr6 cfxr3 cfxr7 cfxr0 cfxr2 cfxr1 cfxr3 cfxr4 cfxr6 cfxr5 cfxr7 cfxr0 cfxr2 cfxr1 cfxr3 cfxr4 cfxr5 cfxr6 cfxr7 cfxr0 cfxr1 cfxr2 cfxr3 cfxr4 cfxr5 cfxr6 cfxr7 x = filter bank number fscx = 3 fscx = 2 fscx = 1 fscx = 0 filter bank scale configuration 1 these bits are located in the cfcr register filter bank scale config. bits 1 identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. identifier mask/ident. stid10:3 stid2:0 rtr ide exid17:15 exid14:7 exid6:0 bit mapping stid10:3 bit mapping stid10:3 identifier mask/ident. bit mapping stid2:0 rtr ide exid17:15 becan controller (becan) st72561-auto 226/324 doc id 12370 rev 8 to figure 102 . the identifier list or identifier mask mode for the corresponding mask/identifier registers is configured by means of the fmclx and fmchx bits in the cfmr register. the fmclx bit defines the mode for the two least significant bytes, and the fmchx bit the mode for the two most significant bytes of filter bank x. example 1 : if filter bank 1 is configured as two 16-bit filters, then the fmcl1 bit defines the mode of the cf1r2 and cf1r3 registers and the fmch1 bit defines the mode of the cf1r6 and cf1r7 registers. if filter bank 2 is configured as four 8-bit filters, then the fmcl2 bit defines the mode of the cf2r1 and cf2r3 registers and the fmch2 bit defines the mode of the cf2r5 and cf2r7 registers. note: in 32-bit configuration, the fmclx and fmchx bits must have the same value to ensure that the four mask/identifier registers are in the same mode. to filter a group of identifiers, configure the mask/identifier registers in mask mode. to select single identifiers, configure the ma sk/identifier registers in identifier list mode. filters not used by the application should be left deactivated. filter match index once a message has been received in the fifo it is available to the application. typically application data are copied into ram locations. to copy the data to the right location the application has to identify the data by means of the identifier. to avoid this and to ease the access to the ram locations, the can co ntroller provides a filter match index. this index is stored in the mailbox together with the message according to the filter priority rules. thus each received message has its associated filter match index. the filter match index can be used in two ways: compare the filter match index with a list of expected values. use the filter match index as an index on an array to access the data destination location. for non-masked filters, the software no longer has to compare the identifier. if the filter is masked the software reduces the comparison to the masked bits only. filter priority rules depending on the filter combination it may occur that an identifier passes successfully through several filters. in this case the filter match value stored in the receive mailbox is chosen according to the following rules: a filter in identifier list mode prevails on an filter in mask mode. a filter with full identifier coverage prevails over filters covering part of the identifier, e.g. 16-bit filters preva il over 8-bit filters. filters configured in the same mode and with identical coverage are prioritized by filter number and register number. the lower the number the higher the priority. st72561-auto becan controller (becan) doc id 12370 rev 8 227/324 figure 103. filtering mechanism - example the example above shows the filtering principle of the becan. on reception of a message, the identifier is compared first with the filters configured in identifier list mode. if there is a match, the message is stored in the fifo and the index of the matching filter is stored in the filter match index. as shown in the example, the identifier matches with identifier #2 thus the message content and mfmi 2 is stored in the fifo. if there is no match, the incoming identifier is then compared with the filters configured in mask mode. if the identifier does not match any of the identifiers configured in the filters, the message is discarded by hardware without software intervention. 17.4.4 message storage the interface between the software and the hardware for the can messages is implemented by means of mailboxes. a mailbox contains all information related to a message; identifier, data, control and status information. transmit mailbox the software sets up the message to be transmitted in an empty transmit mailbox. the status of the transmission is indicated by hardware in the mcsr register. identifier list message discarded identifier & mask identifier 0 identifier 1 identifier 2 identifier n identifier n+1 mask identifier n+m mask identifier message received ctrl data identifier #2 match message stored receive fifo no match found n: number of single identifiers to receive m: number of identifier groups to receive n and m values depend on the configuration of the filters becan controller (becan) st72561-auto 228/324 doc id 12370 rev 8 receive mailbox when a message has been received, it is available to the software in the fifo output mailbox. once the software has handled the message (e.g. read it) the software must release the fifo output mailbox by means of the rfom bit in the crfr register to make the next incoming message available. the filter match index is stored in the mfmi register. table 82. transmit mailbox mapping offset to transmit mailbox base address (bytes) register name 0mcsr 1 mdlc 2 midr0 3 midr1 4 midr2 5 midr3 6mdar0 7mdar1 8mdar2 9mdar3 10 mdar4 11 mdar5 12 mdar6 13 mdar7 14 reserved 15 reserved table 83. receive mailbox mapping offset to receive mailbox base address (bytes) register name 0mfmi 1mdlc 2 midr0 3 midr1 4 midr2 5 midr3 6mdar0 7mdar1 8mdar2 9mdar3 st72561-auto becan controller (becan) doc id 12370 rev 8 229/324 figure 104. can error state diagram 17.4.5 error management the error management as described in the can protocol is handled entirely by hardware using a transmit error counter (tecr register) and a receive error counter (recr register), which get incremented or decremented according to the error condition. for detailed information about tec and rec management, please refer to the can standard. both of them may be read by software to determine the stabilit y of the network. furthermore, the can hardware provides detailed information on the current error status in cesr register. by means of ceier register a nd errie bit in cier register, the software can configure the interrupt generation on error detection in a very flexible way. bus-off recovery the bus-off state is reached when tecr is greater then 255, this state is indicated by boff bit in cesr register. in bus-off state, the becan acts as disconnected from the can bus, hence it is no longer able to transmit and receive messages. depending on the abom bit in the cmcr register becan will recover from bus-off (become error active again) either automatically or on software request. but in both cases the becan has to wait at least for the recovery sequence specified in the can standard (128 x 11 consecutive recessive bits monitored on canrx). 10 mdar4 11 mdar5 12 mdar6 13 mdar7 14 reserved 15 reserved table 83. receive mailbox mapping (continued) offset to receive mailbox base address (bytes) register name error passive when tec or rec > 127 when tec and rec < 128, error active bus off when tec > 255 when 128 * 11 recessive bits occur: becan controller (becan) st72561-auto 230/324 doc id 12370 rev 8 if abom is set, the becan will start the recove ring sequence automatically after it has entered bus-off state. if abom is cleared, the software must initiate the recovering sequence by requesting becan to enter initialization mode. then becan starts monitoring the recovery sequence when the becan is requested to leave the initialization mode. note: in initialization mode, becan does not monitor the canrx signal, therefore it cannot complete the recovery sequence. to recover, becan must be in normal mode. 17.4.6 bit timing the bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the star t-bit edge and resynchronizing on the following edges. its operation may be explained simply by splitting nominal bit time into three segments as follows: synchronization segment (sync_seg): a bit change is expected to occur within this time segment. it has a fixed length of one time quantum (1 x t can ). bit segment 1 (bs1): defines the location of the sample point. it includes the prop_seg and phase_seg1 of the can standard. its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compensate for positive phase drifts due to differences in the frequency of the various nodes of the network. bit segment 2 (bs2): defines the location of the transmit po int. it represen ts the phase_seg2 of the can standard. its duration is programmable between 1 and 8 time quanta but may also be automatically shortened to compensate for negative phase drifts. resynchronization jump width (rjw): defines an upper bound to the amount of lengthening or shortening of the bit segments. it is programmable between 1 and 4 time quanta. to guarantee the correct behavior of the can controller, sync_seg + bs1 + bs2 must be greater than or equal to 5 time quanta. for a detailed description of the can resynchronization mechanism and other bit timing configuration constraints, please refer to the bosch can standard 2.0. as a safeguard against programming errors, t he configuration of the bit timing registers cbtr1 and cbtr0 is only possible while the device is in initialization mode. figure 105. bit timing sync_seg bit segment 1 (bs1) bit segment 2 (bs2) nominal bit time 1 x t can t bs1 t bs2 sample point transmit point st72561-auto becan controller (becan) doc id 12370 rev 8 231/324 figure 106. can frames (part 1/2) figure 107. can frames (part 2/2) data field 8 * n control field 6 arbitration field 12 crc field 16 ack field 7 sof id dlc crc data frame (standard identifier) 44 + 8 * n ack 2 inter-frame space or overload frame inter-frame space rtr ide r0 eof data field 8 * n ctrl field 6 12 crc field 16 ack field 7 sof id dlc crc data frame (extended identifier) 64 + 8 * n arbitration field 12 rtr ide r0 sof id dlc remote frame 44 crc field 16 7 crc control field 6 overload flag 6 overload delimiter 8 overload frame error flag 6 error delimiter 8 error frame flag echo 6 bus idle inter-frame space suspend 8 intermission 3 transmission ack ack 2 2 inter-frame space or overload frame inter-frame space inter-frame space or overload frame inter-frame space inter-frame space or overload frame data frame or remote frame notes: 0 <= n <= 8 sof = start of frame id = identifier rtr = remote transmission request ide = identifier extension bit r0 = reserved bit dlc = data length code crc = cyclic redundancy code error flag: 6 dominant bits if node is error active else 6 recessive bits. suspend transmission: applies to error passive nodes only. eof = end of frame ack = acknowledge bit data frame or remote frame any frame inter-frame space or error frame end of frame or error delimiter or overload delimiter ack field end of frame srr ide eof rtr r1 r0 std arbitr. field 20 ext arbitr. field becan controller (becan) st72561-auto 232/324 doc id 12370 rev 8 17.5 interrupts two interrupt vectors are dedicated to becan. each interrupt source can be independently enabled or disabled by means of the can interrupt enable register (cier) and can error interrupt enable register (ceier). figure 108. event flags and interrupt generation the fifo interrupt can be generated by the following events: ? reception of a new message, fmp bits in the crfr0 register incremented. ? fifo0 full condition, full bit in the crfr0 register set. ? fifo0 overrun condition, fovr bit in the crfr0 register set. the transmit, error and status change interrupt can be generated by the following events: ? transmit mailbox 0 becomes empty, rqcp0 bit in the ctsr register set. ? transmit mailbox 1 becomes empty, rqcp1 bit in the ctsr register set. ? error condition, for more details on error conditions please refer to the can error status register (cesr). ? wake-up condition, sof monitored on the can rx signal. 17.6 register access protection erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole can network. therefore the following registers can be modified by software only while the hardware is in initialization mode: cbtr0, cbtr1, cfcr0, cfcr1, cfmr and cdgr registers. rqcp rqcp mcsr + tmeie cier transmit/ & ewgf ewgie epvf epvie boff bofie lecief lecie & & & & cesr + & errie fmp & fmpie full & ffie fovr & fovie + crfr fifo interrupt wkui & wkuie cmsr txmb 0 txmb 1 + interrupt error/ status change st72561-auto becan controller (becan) doc id 12370 rev 8 233/324 although the transmission of incorrect data will not cause problems at the can network level, it can severely disturb the application. a transmit mailbox can be only modified by software while it is in empty state (refer to figure 100 ). the filters must be deactivated before their value can be modified by software. the modification of the filter configuration (scale or mode) can be done by software only in initialization mode. 17.7 becan cell limitations 17.7.1 fifo corruption fifo corruption occurs in the following case: when the becan rx fifo already holds two messages (that is, fmp == 2) and the application releases the fifo (with the instruction crfr = b_rfom;) while the becan requests the transfer of a new receive message into the fifo (this lasts one cpu cycle) then the internal fifo pointer is not updated but the fmp bits are updated correctly as the fifo pointer is not updated correctly, this causes the last message received to be overwritten by any incoming message. this means one message is lost as shown in the example in figure 109 . the becan will not recover normal operation until a device reset occurs. becan controller (becan) st72561-auto 234/324 doc id 12370 rev 8 figure 109. fifo corruption workaround to implement the workaround, use the following sequence to release the can receive fifo. this sequence replaces any occurrence of crfr |= b_rfom; . figure 110. workaround 1 explanation of workaround 1 first, we need to make sure no interrupt can occur between the test and the release of the fifo to avoid any added delay. the workaround checks if the first two fifo levels are already full (fmp = 2) as the problem happens only in this case. if fmp 2 we release the fifo immediately, if fmp = 2, we monitor the reception status of the cell. the reception status is available in the cmsr register bit 5 (rec bit). note: the rec bit was called rx in older versions of the datasheet. if the cell is not receiving, then rec bit in cmsr is at 0, the software can release the fifo immediately: there is no risk. if the cell is receiving, it is important to make sure the releas e of the mailbox will not happen at the time when the received message is loaded into the fifo. initial state * v * pointer to next receive location v pointer to next message to be released --- when the fifo is empty, v and * point to the same location fifo receive message a * v a- - receive message b ab- * v receive message c abc * v * does not move because fifo is full (normal operation) release message a abc v * release message b dbc and receive message d * v dbc * normal operation * does not move, pointer corruption receive message e ebc release message c ebc * v release message e ebc * v c released * v release message b ebc * v * and v are not pointing to the same message d is overwritten by e fmp 0 1 2 3 2 2 3 2 1 0 the fifo is empty v e released instead of b if ((crfr & 0x03) == 0x02) while ((cmsr & 0x20) && (cdgr & 0x08)) { }; crfr |= b_rfom; st72561-auto becan controller (becan) doc id 12370 rev 8 235/324 we could simply wait for the end of the reception, but this could take a long time (200s for a 100-bit frame at 500 khz), so we also monitor the rx pin of the microcontroller to minimize the time the application may wait in the while loop. we know the critical window is located at the end of the frame, 6+ can bit times after the acknowledge bit (exactly six full bit times plus the time from the beginning of the bit to the sample point). those bits represent the acknowledge delimiter + the end of frame slot. we know also that those 6+ bits are in recessive state on the bus, therefore if the can rx pin of the device is at ?0?, (reflecting a can dominant state on the bus), this is early enough to be sure we can release the fifo before the critical time slot. therefore, if the device hardware pin rx is at 0 and there is a reception on going, its message will be transferred to the fifo only 6+ can bit times la ter at the earliest (if the dominant bit is the acknowledge) or later if the dominant bit is part of the message. compiled with cosmic c compiler, the workaround generates the following assembly lines: in the worst case configuration, if the can cell speed is set to the maximum baud rate, one bit time is 8 cpu cycle. in this case the minimum time between the end of the acknowledge and the critical period is 52 cpu cycles (48 for the 6 bit times + 4 for the (prop seg + t seg1 ). according to the previous code timing, we need less than 15 cycles from the time we see the dominant state to the time we perform the fifo release (one full loop + the actual release) therefore the application will never release the fifo at the critical time when this workaround is implemented. timing analysis time spent in the workaround inside a can frame, the longest period that the rx pin stays in recessive state is 5 bits. at the end of the frame, the time between the acknowledge dominant bit and the end of reception (signaled by rec bit status) is 8t canbit , therefore the maximum time spent in the workaround is: 8t canbit +t loop +t test +t release in this case or 8t canbit +25t cpu . at low speed, this time could represent a long delay for the application, therefore it makes sense to evaluate how frequently this delay occurs. in order to reach the critical fmp = 2, the can node needs to receive two messages without servicing them. then in order to reach the crit ical window, the cell has to receive a third one and the application has to release the mailbox at the same time, at the end of the reception. in the application, messages are not processed only if either the interrupt are disabled or higher level interrupts are being serviced. cycles if ((crfr & 0x03) == 0x02) ld a, crfr 3 and a,#3 2 cp a,#2 2 jrne _release 3 test: 10 cycles while ((cmsr & 0x20) && (cdgr & 0x08)) { }; _whileloop: btjf cmsr,#5,_release 5 btjt cdgr,#3,_whileloop 5 loop: 10 cycles crfr |= b_rfom; _release: bset crfr,#5 5 release: 5 cycles becan controller (becan) st72561-auto 236/324 doc id 12370 rev 8 therefore if: t it higher level + t it disable + t it can < 2 x t can frame the application will never wait in the workaround t it higher level : this the sum of the duration of all the interrupts with a level strictly higher than the can interrupt level t it disable : this is the longest time the application di sables the can interrup t (or all interrupts) t it can : this is the maximum duration between the beginning of the can interrupt and the actual location of the workaround t can frame : this is minimum can frame duration figure 111. critical window timing diagram figure 112. reception of a sequence of frames side-effect of workaround 1 because the while loop lasts 10 cpu cycles, at high baud rate, it is possible to miss a dominant state on the bus if it lasts just one can bit time and the bus speed is high enough (see ta b l e 8 4 ). if this happens, we will continue waiting in th e while loop instead of releasing the fifo immediately. the workaround is still valid be cause we will not release the fifo during the table 84. while loop timing f cpu software timing: while loop minimum baud rate for possible missed dominant bit 8 mhz 1.25 s 800 kbaud 4 mhz 2.5 s 400 kbaud f cpu 10/f cpu f cpu /10 a release is not allowed at this time critical window: the received message is placed in the fifo can frame acknowledge: last dominant bit in the frame time to test rx pin and to release the fifo 4.5s@4 mhz time between the end of the acknowledge and the critical windows - 6 full can bit times + time to the sample point approx. 13s @ 500 kbaud 0 122 t can frame 1t can frame 2t can frame 3 fmp bus cpu t it disable t it higher level t it can st72561-auto becan controller (becan) doc id 12370 rev 8 237/324 critical period. but the applicat ion may lose additional time wait ing in the while loop as we are no longer able to guarantee a maximum of 6 can bit times spent in the workaround. in this particular case the time the application can spend in the workaround may increase up to a full can frame, depending of the frame contents. this case is very rare but happens when a specific sequence is present on in the can frame. the example in figure 113 shows reception at maximum can baud rate: in this case t can is 8/f cpu and the sampling time is 10/f cpu . if the application is using the maximum baud rate and the possible delay caused by the workaround is not acceptable, there is another workaround which reduces the rx pin sampling time. workaround 2 (see figure 114 ) first tests that fmp = 2 and the can cell is receiving, if not the fifo can be released immediately. if yes, the program goes through a sequence of test instructions on the rx pin that last longer than the time between the acknowledge dominant bit and the critical time slot. if the rx pin is in recessive state for more than 8 can bit times, it means we are now after the acknowledge and the critical slot. if a dominant bit is read on the bus, we can release the fifo immediately. this workaround has to be written in assembly language to avoid the compiler optimizing the test sequence. the implementation shown here is for the can bus maximum speed (1 mbaud @ 8 mhz cpu clock). figure 113. reception at maximum can baud rate figure 114. workaround 2 rd can bus signal sampling of rx pin dddd r r r rr r r rr r r rr r r rr r r ld a, crfr and a,#3 cp a,#2 ; test fmp=2 ? jrne _release ; if not release btjf cmsr,#5,_release ; test if reception on going. ; if not release btjf cdgr,#3,_release ; sample rx pin for 8 can bit time btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release btjf cdgr,#3,_release _release: bset crfr,#5 becan controller (becan) st72561-auto 238/324 doc id 12370 rev 8 17.8 register description 17.8.1 control and status registers can master control register (cmcr) reset value: 0000 0010 (02h) bit 7 = reserved, must be kept cleared. bit 6 = abom automatic bus-off management read/set/clear this bit controls the behaviour of the can hardware on leaving the bus-off state. 0: the bus-off state is left on software request. refer to error management , bus-off recovery. 1: the bus-off state is left automatically by hardware once 128 x 11 recessive bits have been monitored. for detailed information on the bus-off state please refer to error management . bit 5 = awum automatic wake-up mode read/set/clear this bit controls the behaviour of the can hardware on message reception during sleep mode. 0: the sleep mode is left on software request by cleari ng the sleep bit of the cmcr register. 1: the sleep mode is left automatically by hardware on can message detection. the sleep bit of the cmcr register and the slak bi t of the cmsr register are cleared by hardware. bit 4 = nart no automatic retransmission read/set/clear 0: the can hardware will automatically retransmit the messag e until it has been successfully transmitted according to the can standard. 1: a message will be transmitted only once, independently of the transmission result (successful, error or arbitration lost). bit 3 = rflm receive fifo locked mode read/set/clear 0: receive fifo not locked on overrun. once a receive fifo is full the next incoming message will overwrite the previous one. 1: receive fifo locked against overrun. once a receive fifo is full the next incoming message will be discarded. bit 2 = txfp transmit fifo priority read/set/clear 7 0 0 abom awum nart rflm txfp sleep inrq st72561-auto becan controller (becan) doc id 12370 rev 8 239/324 this bit controls the transmission order when several mailboxes are pending at the same time. 0: priority driven by the identifier of the message 1: priority driven by the request order (chronologically) bit 1 = sleep sleep mode request read/set/clear this bit is set by software to request the can hardware to enter the sleep mode. sleep mode will be entered as soon as the current ca n activity (transmission or reception of a can frame) has been completed. this bit is cleared by software to exit sleep mode. this bit is cleared by hardware when the awum bit is set and a sof bit is detected on the can rx signal. bit 0 = inrq initialization request read/set/clear the software clears this bit to switch the hardware into normal mode. once 11 consecutive recessive bits have been monitored on the rx signal the can hardware is synchronized and ready for transmission and reception. hardware signals this event by clearing the inak bit if the cmsr register. software sets this bit to request the can hardware to enter initialization mode. once software has set the inrq bit, the can hardware waits until the current can activity (transmission or reception) is completed before entering the initialization mode. hardware signals this event by setting the inak bit in the cmsr register. can master status register (cmsr) reset value: 0000 0010 (02h) note: to clear a bit of this register the software must write this bit with a one. bits 7:4 = reserved. forced to 0 by hardware. bit 5 = rec receive read the can hardware is currently receiver. bit 4 = tran tr a n s m i t read the can hardware is cu rrently transmitter. bit 3 = wkui wake-up interrupt read/clear this bit is set by hardware to signal that a sof bit has been detected while the can hardware was in sleep mode. setting this bit generates a status change interrupt if the wkuie bit in the cier register is set. this bit is cleared by software. bit 2 = erri error interrupt read/clear this bit is set by hardware when a bit of the cesr has been set on error detection and the 7 0 0 0 rec tran wkui erri slak inak becan controller (becan) st72561-auto 240/324 doc id 12370 rev 8 corresponding interrupt in the ceier is enabled. setting this bit generates a status change interrupt if the errie bit in the cier register is set. this bit is cleared by software. bit 1 = slak sleep acknowledge read this bit is set by hardware and indicates to the software that the can hardware is now in sleep mode. this bit acknowledges the sleep mode request from th e software (set sleep bit in cmcr register). this bit is cleared by hardware when the can hardware has left sleep mode. sleep mode is left when the sleep bit in the cmcr register is cleared. please refer to the awum bit of the cmcr register description for detail ed information for clearing sleep bit. bit 0 = inak initialization acknowledge read this bit is set by hardware and indicates to the software that the can hardware is now in initialization mode. this bit ac knowledges the initialization request from the software (set inrq bit in cmcr register). this bit is cleared by hardware when the ca n hardware has left the initialization mode and is now synchronized on the can bus. to be synchronized the hardware has to monitor a sequence of 11 consecutive recessive bits on the can rx signal. 17.8.2 can transmit st atus register (ctsr) read/ write reset value: 0000 0000 (00h) note: to clear a bit of this register the software must write this bit with a one. bits 7:6 = reserved. forced to 0 by hardware. bit 5 = txok1 transmission ok for mailbox 1 read this bit is set by hardware when the transmission request on mailbox 1 has been completed successfully. please refer to figure 100 . this bit is cleared by hardware when mailbox 1 is requested for transmission or when the software clears the rqcp1 bit. bit 4 = txok0 transmission ok for mailbox 0 read this bit is set by hardware when the transmission request on mailbox 0 has been completed successfully. please refer to figure 100 . this bit is cleared by hardware when mailbox 0 is requested for transmission or when the software clears the rqcp0 bit. bits 3:2 = reserved. forced to 0 by hardware. bit 1 = rqcp1 request completed for mailbox 1 read/ clear 7 0 00txok1txok000rqcp1rqcp0 st72561-auto becan controller (becan) doc id 12370 rev 8 241/324 this bit is set by hardware to signal that the last request for mailbox 1 has been completed. the request could be a transmit or an abort request. this bit is cleared by software. bit 0 = rqcp0 request completed for mailbox 0 read/ clear this bit is set by hardware to signal that the last request for mailbox 0 has been completed. the request could be a transmit or an abort request. this bit is cleared by software. can transmit priority register (ctpr) all bits of this register are read only. reset value: 0000 1100 (0ch) bit 7 = reserved. forced to 0 by hardware. bit 6 = low1 lowest priority flag for mailbox 1 read this bit is set by hardware when more than one mailbox are pending for transmission and mailbox 1 has the lowest priority. bit 5 = low0 lowest priority flag for mailbox 0 read this bit is set by hardware when more than one mailbox are pending for transmission and mailbox 0 has the lowest priority. note: these bits are set to zero when only one mailbox is pending. bit 4 = reserved. forced to 0 by hardware. bit 3 = tme1 transmit mailbox 1 empty read this bit is set by hardware when no tr ansmit request is pending for mailbox 1. bit 2 = tme0 transmit mailbox 0 empty read this bit is set by hardware when no tr ansmit request is pending for mailbox 0. bit 1:0 = code mailbox code read in case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free. in case all transmit mailboxes are pending, the code value is equal to the number of the transmit mailbox with the lowest priority. 7 0 0 low1 low0 0 tme1 tme0 0 code becan controller (becan) st72561-auto 242/324 doc id 12370 rev 8 can receive fifo registers (crfr) read / write reset value: 0000 0000 (00h) note: to clear a bit in this register, software must write a ?1? to the bit. bits 7:6 = reserved. forced to 0 by hardware. bit 5 = rfom release fifo output mailbox read/set set by software to release the output mailbox of the fifo. the output mailbox can only be released when at least one message is pending in the fifo. setting this bit when the fifo is empty has no effect. if more than one message are pending in the fifo, the software has to release the output mailbox to access the next message. cleared by hardware when the output mailbox has been released. bit 4 = fovr fifo overrun read/ clear this bit is set by hardware when a new message has been received and passed the filter while the fifo was full. this bit is cleared by software. bit 3 = full fifo full read/ clear set by hardware when three messages are stored in the fifo. this bit can be cleared by software writing a one to this bit or releasing the fifo by means of rfom. bit 2 = reserved. forced to 0 by hardware. bits 1:0 = fmp[1:0] fifo message pending read these bits indicate how many messages are pending in the receive fifo. fmp is increased each time the hardware stores a new message in to the fifo. fmp is decreased each time the software releases the output mailbox by setting the rfom bit. can interrupt enable register (cier) read/ write reset value: 0000 0000 (00h) note: all bits of this register are set and cleared by software. 7 0 0 0 rfom fovr full 0 fmp1 fmp0 7 0 wkuie 0 0 0 fovie0 ffie0 fmpie0 tmeie st72561-auto becan controller (becan) doc id 12370 rev 8 243/324 bit 7 = wkuie wake-up interrupt enable 0: no interrupt when wkui is set. 1: interrupt generated when wkui bit is set. bits 6:4 = reserved. forced to 0 by hardware. bit 3 = fovie fifo overrun interrupt enable\ 0: no interrupt when fovr bit is set. 1: interrupt generated when fovr bit is set. bit 2 = ffie fifo full interrupt enable 0: no interrupt when full bit is set. 1: interrupt generated when full bit is set. bit 1 = fmpie fifo message pending interrupt enable 0: no interrupt on fmp[1:0] bits transition from 00b to 01b. 1: interrupt generated on fmp[1:0] bits transition from 00b to 01b. bit 0 = tmeie transmit mailbox empty interrupt enable 0: no interrupt when rqcpx bit is set. 1: interrupt generated when rqcpx bit is set. can error status register (cesr) read/ write reset value: 0000 0000 (00h) bit 7 = reserved. forced to 0 by hardware. bits 6:4 = lec[2:0] last error code read/ set/ clear this field holds a code which indicates the type of the last error detected on the can bus. if a message has been transferred (reception or transmission) wit hout error, this field will be cleared to ?0?. the code 7 is unused and may be written by the cpu to check for update 7 0 0 lec2 lec1 lec0 0 boff epvf ewgf table 85. lec error types code error type 0no error 1 stuff error 2 form error 3 acknowledgment error 4 bit recessive error 5 bit dominant error 6 crc error 7 set by software becan controller (becan) st72561-auto 244/324 doc id 12370 rev 8 bit 3 = reserved. forced to 0 by hardware. bit 2 = boff bus-off flag read this bit is set by hardware when it enters the bus-off state. the bus-off state is entered on tecr overrun, tec greater than 255, refer to error management . bit 1 = epvf error passive flag read this bit is set by hardware when the error passive limit has been reached (receive error counter or transmit error counter greater than 127). bit 1 = ewgf error warning flag read this bit is set by hardware when the warning limit has been reached. receive error counter or transmit error counter greater than 96. can error interrupt enable register (ceier) read/ write reset value: 0000 0000 (00h) note: all bits of this register are set and clear by software. bit 7 = errie error interrupt enable 0: no interrupt will be genera ted when an error condition is pending in the cesr. 1: an interrupt will be genera tion when an error condition is pending in the cesr. bits 6:5 = reserved. forced to 0 by hardware. bit 4 = lecie last error code interrupt enable 0: erri bit will not be set when the error co de in lec[2:0] is set by hardware on error detection. 1: erri bit will be set when the error code in lec[2:0] is set by hardware on error detection. bit 3 = reserved. forced to 0 by hardware. bit 2 = bofie bus-off interrupt enable 0: erri bit will not be set when boff is set. 1: erri bit will be set when boff is set. bit 1 = epvie error passive interrupt enable 0: erri bit will not be set when epvf is set. 1: erri bit will be set when epvf is set. bit 0 = ewgie error warning interrupt enable 0: erri bit will not be set when ewgf is set. 1: erri bit will be set when ewgf is set. 7 0 errie 0 0 lecie 0 bofie epvie ewgie st72561-auto becan controller (becan) doc id 12370 rev 8 245/324 transmit error counter register (tecr) read only reset value: 0000 0000 (00h) tec[7:0] is the least significant byte of the 9-bit transmit error counter implementing part of the fault confinement mechanism of the can protocol. receive error counter register (recr) page: 00h ? read only reset value: 0000 0000 (00h) rec[7:0] is the receive error counter implementing part of the fault confinement mechanism of the can protocol. in case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the can standard. after every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. when the counter value exceeds 127, the can controller enters the error passive state. can diagnosis register (cdgr) read/ write reset value: 0000 1100 (0ch) note: all bits of this register are set and cleared by software. bit 3 = rx can rx signal read monitors the actual value of the can_rx pin. bit 2 = samp last sample point read the value of the last sample point. bit 1 = silm silent mode read/set/clear 0: normal operation 1: silent mode 7 0 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 7 0 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 7 0 0000rxsampsilmlbkm becan controller (becan) st72561-auto 246/324 doc id 12370 rev 8 bit 0 = lbkm loop back mode read/set/clear 0: loop back mode disabled 1: loop back mode enabled can bit timing register 0 (cbtr0) read/ write reset value: 0000 0000 (00h) note: this register can only be accessed by the software when the can hardware is in configuration mode. bit 7:6 sjw[1:0] resynchronization jump width these bits define the maximum number of time quanta the can hardware is allowed to lengthen or shorten a bit to perform the resynchronization. resynchronization jump width = (sjw+1). bit 5:0 brp[5:0] baud rate prescaler these bits define the length of a time quantum. tq = (brp+1)/f cpu for more information on bit timing, please refer to bit timing . 7 0 sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 st72561-auto becan controller (becan) doc id 12370 rev 8 247/324 can bit timing register 1 (cbtr1) read/ write reset value: 0001 0011 (23h) bit 7 = reserved. forced to 0 by hardware. bits 6:4 bs2[2:0] time segment 2 these bits define the number of time quanta in time segment 2. time segment 2 = (bs2+1) bits 3:0 bs1[3:0] time segment 1 these bits define the number of time quanta in time segment 1 time segment 1 = (bs1+1) for more information on bit timing, please refer to bit timing . can filter page select register (cpsr) read/ write reset value: 0000 0000 (00h) note: all bits of this register are set and cleared by software. bits 7:3 = reserved. forced to 0 by hardware. bits 2:0 = ps[2:0] page select read/ write this register contains the page number. 7 0 0 bs22 bs21 bs20 bs13 bs12 bs11 bs10 7 0 0 0 0 0 0 fps2 fps1 fps0 table 86. filter page selection ps[2:0] page selected 0 tx mailbox 0 1 tx mailbox 1 2 acceptance filter 0:1 3 acceptance filter 2:3 4 acceptance filter 4:5 5 reserved 6 configuration/diagnosis 7 receive fifo becan controller (becan) st72561-auto 248/324 doc id 12370 rev 8 17.8.3 mailbox registers this chapter describes the registers of the transmit and receive mailboxes. refer to message storage for detailed register mapping. transmit and receive mailboxes have the same registers except: mcsr register in a transmit mailbox is replaced by mfmi register in a receive mailbox. a receive mailbox is always write protected. a transmit mailbox is write enable only while empty, corresponding tme bit in the ctpr register set. mailbox control status register (mcsr) read/ write reset value: 0000 0000 (00h) bits 7:6 = reserved. forced to 0 by hardware. bit 5 = terr transmission error read this bit is updated by hardware after each transmission attempt. 0: the previous transmission was successful 1: the previous transmission failed due to an error bit 4 = alst arbitration lost read this bit is updated by hardware after each transmission attempt. 0: the previous transmission was successful 1: the previous transmission failed due to an arbitration lost bit 3 = txok transmission ok read the hardware updates this bit after each transmission attempt. 0: the previous transmission failed 1: the previous transmission was successful note: this bit has the same value as the corresponding txokx bit in the ctsr register. bit 2 = rqcp request completed read/ clear set by hardware when the last request (transmit or abort) has been performed. cleared by software writing a ?1? or by hardware on transmission request. note: this bit has the same value as the corresponding rqcpx bit of the ctsr register. clearing this bit clears all the status bits (txok, alst and terr) in the mcsr register and the rqcp and txok bits in the ctsr register. bit 1 = abrq abort request for mailbox read/ set set by software to abort the transmission request for the corresponding mailbox. 7 0 0 0 terr alst txok rqcp abrq txrq st72561-auto becan controller (becan) doc id 12370 rev 8 249/324 cleared by hardware when the mailbox becomes empty. setting this bit has no effect when the mailbox is not pending for transmission. bit 0 = txrq transmit mailbox request read/ set set by software to request the transmission for the corresponding mailbox. cleared by hardware when the mailbox becomes empty. note: this register is implemented only in tran smit mailboxes. in rece ive mailboxes, the mfmi register is mapped at this location. mailbox filter match index (mfmi) this register is read only. reset value: 0000 0000 (00h) bits 7:0 = fmi[7:0] filter match index this register contains the index of the filter the message stored in the mailbox passed through. for more details on identifier filtering please refer to identifier filtering - filter match index paragraph. note: this register is implemented only in rece ive mailboxes. in transmit mailboxes, the mcsr register is mapped at this location. mailbox identifier registers (midr[3:0]) read/ write reset value: undefined midr0 bit 7 = reserved. forced to 0 by hardware. bit 6 = ide extended identifier this bit defines the identifier type of message in the mailbox. 0: standard identifier. 1: extended identifier. bit 5 = rtr remote transmission request 0: data frame 1: remote frame bits 4:0 = stid[10:6] standard identifier 5 most significant bits of the standard part of the identifier. 7 0 fmi7 fmi6 fmi5 fmi4 fmi3 fmi2 fmi1 fmi0 7 0 0 ide rtr stid10 stid9 stid8 stid7 stid6 becan controller (becan) st72561-auto 250/324 doc id 12370 rev 8 midr1 bits 7:2 = stid[5:0] standard identifier 6 least significant bits of the standard part of the identifier. bits 1:0 = exid[17:16] extended identifier 2 most significant bits of the extended part of the identifier. midr2 bits 7:0 = exid[15:8] extended identifier bits 15 to 8 of the extended part of the identifier. midr3 bits 7:1 = exid[6:0] extended identifier 6 least significant bits of the extended part of the identifier. mailbox data length control register (mdlc) read / write reset value: xxxx xxxx (xxh) note: all bits of this register is write protected when the mailbox is not in empty state. bit 7 = reserved, must be kept cleared. bits 6:4 = reserved, forced to 0 by hardware. bits 3:0 = dlc[3:0] data length code this field defines the number of data bytes a data frame contains or a remote frame request. mailbox data registers (mdar[7:0]) read / write reset value: undefined note: all bits of this register are write protected when the mailbox is not in empty state. 7 0 stid5 stid4 stid3 stid2 stid1 stid0 exid17 exid16 7 0 exid15 exid14 exid13 exid12 exid11 exid10 exid9 exid8 7 0 exid7 exid6 exid5 exid4 exid3 exid2 exid1 exid0 7 0 0 0 0 0 dlc3 dlc2 dlc1 dlc0 7 0 data7 data6 data5 data4 data3 data2 data1 data0 st72561-auto becan controller (becan) doc id 12370 rev 8 251/324 bits 7:0 = data[7:0] data a data byte of the message. a message can contain from 0 to 8 data bytes. 17.8.4 can filter registers can filter configuration register 0 (cfcr0) read / write reset value: 0000 0000 (00h) note: all bits of this register are set and cleared by software. to modify the ffax and fscx bits, the becan must be in init mode. bit 7 = reserved. forced to 0 by hardware. bits 6:5 = fsc1[1:0] filter scale configuration these bits define the scale configuration of filter 1. bit 4 = fact1 filter active the software sets this bit to activate filter 1. to modify the filter 1 registers (cf1r[7:0]), the fact1 bit must be cleared. 0: filter 1 is not active 1: filter 1 is active bit 3 = reserved. forced to 0 by hardware. bits 2:1 = fsc0[1:0] filter scale configuration these bits define the scale configuration of filter 0. bit 0 = fact0 filter active the software sets this bit to activate filter 0. to modify the filter 0 registers (cf0r[0:7]), the fact0 bit must be cleared. 0: filter 0 is not active 1: filter 0 is active can filter configuration register 1 (cfcr1) read/ write reset value: 0000 0000 (00h) note: all bits of this register are set and cleared by software. bit 7 = reserved. forced to 0 by hardware. bits 6:5 = fsc3[1:0] filter scale configuration these bits define the scale configuration of filter 3. 7 0 0 fsc11 fsc10 fact1 0 fsc01 fsc00 fact0 7 0 0 fsc31 fsc30 fact3 0 fsc21 fsc20 fact2 becan controller (becan) st72561-auto 252/324 doc id 12370 rev 8 bit 4 = fact3 filter active the software sets this bit to activate filter 3. to modify the filter 3 registers (cf3r[0:7]) the fact3 bit must be cleared. 0: filter 3 is not active 1: filter 3 is active bit 3 = reserved. forced to 0 by hardware. bits 2:1 = fsc2[1:0] filter scale configuration these bits define the scale configuration of filter 2. bit 0 = fact2 filter active the software sets this bit to activate filter 2. to modify the filter 2 registers (cf2r[0:7]), the fact2 bit must be cleared. 0: filter 2 is not active 1: filter 2 is active can filter configuration register 2(cfcr2) read/ write reset value: 0000 0000 (00h) note: all bits of this register are set and cleared by software. bit 7 = reserved. forced to 0 by hardware. bits 6:5 = fsc5[1:0] filter scale configuration these bits define the scale configuration of filter 5. bit 4 = fact5 filter active the software sets this bit to activate filter 5. to modify the filter 5 registers (cf5r[0:7]) the fact5 bit must be cleared. 0: filter 5 is not active 1: filter 5 is active bit 3 = reserved. forced to 0 by hardware. bits 2:1 = fsc4[1:0] filter scale configuration these bits define the scale configuration of filter 4. bit 0 = fact4 filter active the software sets this bit to activate filter 4. to modify the filter 4 registers (cf4r[0:7]), the fact4 bit must be cleared. 0: filter 4 is not active 1: filter 4 is active 7 0 0 fsc51 fsc50 fact5 0 fsc41 fsc40 fact4 st72561-auto becan controller (becan) doc id 12370 rev 8 253/324 can filter mode register (cfmr0) read/ write reset value: 0000 0000 (00h) note: all bits of this register are set and cleared by software. bit 7 = fmh3 filter mode high mode of the high registers of filter 3. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 6 = fml3 filter mode low mode of the low registers of filter 3. 0: low registers are in mask mode 1: low registers are in identifier list mode bit 5 = fmh2 filter mode high mode of the high registers of filter 2. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 4 = fml2 filter mode low mode of the low registers of filter 2. 0: low registers are in mask mode 1: low registers are in identifier list mode bit 3 = fmh1 filter mode high mode of the high registers of filter 1. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 2 = fml1 filter mode low mode of the low registers of filter 1. 0: low registers are in mask mode 1: low registers are in identifier list mode bit 1 = fmh0 filter mode high mode of the high registers of filter 0. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 0 = fml0 filter mode low mode of the low registers of filter 0. 0: low registers are in mask mode 1: low registers are in identifier list mode can filter mode register (cfmr1) read/ write 7 0 fmh3 fml3 fmh2 fml2 fmh1 fml1 fmh0 fml0 becan controller (becan) st72561-auto 254/324 doc id 12370 rev 8 reset value: 0000 0000 (00h) note: all bits of this register are set and cleared by software. bits 7:4 = reserved. forced to 0 by hardware. bit 3 = fmh5 filter mode high mode of the high registers of filter 5. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 2 = fml5 filter mode low mode of the low registers of filter 5. 0: low registers are in mask mode 1: low registers are in identifier list mode bit 1 = fmh4 filter mode high mode of the high registers of filter 4. 0: high registers are in mask mode 1: high registers are in identifier list mode bit 0 = fml4 filter mode low mode of the low registers of filter 4. 0: low registers are in mask mode 1: low registers are in identifier list mode filter x register[7:0] (cfxr[7:0]) read/ write reset value: undefined in all configurations: bits 7:0 = fb[7:0] filter bits identifier each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: dominant bit is expected 1: recessive bit is expected mask each bit of the register specifies whether the bit of the associated identifier register must match with the corresponding bit of the expected identifier or not. 0: don?t care, the bit is not used for the comparison 1: must match, the bit of the incoming identifier must have the same level has specified in the corresponding identifier register of the filter. 7 0 0 0 0 0 fmh5 fml5 fmh4 fml4 7 0 fb7 fb6 fb5 fb4 fb3 fb2 fb1 fb0 st72561-auto becan controller (becan) doc id 12370 rev 8 255/324 note: each filter x is composed of 8 registers, cfxr[7:0]. depending on the scale and mode configuration of the filter the function of each register can differ. for the filter mapping, functions description and mask registers association, refer to section identifier filtering . a mask/identifier register in mask mode has the same bit mapping as in identifier list mode. note: to modify these registers, the corresponding fact bit in the cfcr register must be cleared. figure 115. can re gister mapping 68h 69h can master control register can master status register can transmit status register can transmit priority register cmcr cmsr ctsr ctpr can receive fifo register crfr can interrupt enable register can diagnosis register cier cdgr can page selection register cpsr 6ah 6bh 6ch 6dh 6eh 6fh xxh paged register 0 paged register 1 paged register 2 paged register 3 paged register 4 paged register 5 paged register 6 paged register 7 paged register 8 paged register 9 paged register 10 paged register 11 paged register 12 paged register 13 paged register 14 paged register 15 becan controller (becan) st72561-auto 256/324 doc id 12370 rev 8 figure 116. page mapping for can 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh page 0 page 1 page 2 page 3 tx mailbox 0 tx mailbox 1 acceptance filter 0:1 acceptance filter 2:3 mcsr mdlc mtslr mtshr midr0 midr1 midr2 midr3 mdar0 mdar1 mdar2 mdar3 mdar4 mdar5 mdar6 mdar7 mcsr mdlc mtslr mtshr midr0 midr1 midr2 midr3 mdar0 mdar1 mdar2 mdar3 mdar4 mdar5 mdar6 mdar7 cf0r0 cf0r1 cf0r2 cf0r3 cf0r4 cf0r5 cf0r6 cf0r7 cf1r0 cf1r1 cf1r2 cf1r3 cf1r4 cf1r5 cf1r6 cf1r7 cf2r0 cf2r1 cf2r2 cf2r3 cf2r4 cf2r5 cf2r6 cf2r7 cf3r0 cf3r1 cf3r2 cf3r3 cf3r4 cf3r5 cf3r6 cf3r7 mfmi mdlc mtslr mtshr page 7 receive fifo midr0 midr1 midr2 midr3 mdar0 mdar1 mdar2 mdar3 mdar4 mdar5 mdar6 mdar7 page 6 configuration/diagnosis cesr ceier reserved reserved tecr recr btcr0 btcr1 reserved reserved cfmr0 cfmr1 cfcr0 cfcr1 cfcr2 reserved page 4 acceptance filter 4:5 cf4r0 cf4r1 cf4r2 cf4r3 cf4r4 cf4r5 cf4r6 cf4r7 cf5r0 cf5r1 cf5r2 cf5r3 cf5r4 cf5r5 cf5r6 cf5r7 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh st72561-auto becan controller (becan) doc id 12370 rev 8 257/324 table 87. becan control and status page - register map and reset values address (hex.) register name 7 6 5 4 3 2 1 0 68h cmcr reset value 0 abom 0 awum 0 nart 0 rflm 0 txfp 0 sleep 1 inrq 0 69h cmsr reset value 0 0 rec 0 tran 0 wkui 0 erri 0 slak 1 inak 0 6ah ctsr reset value 0 0 txok1 0 txok0 000 rqcp1 0 rqcp0 0 6bh ctpr reset value 0 low1 0 low0 01 tme1 1 tme0 10 code0 0 6ch crfr reset value 0 0 rfom 0 fovr 0 full 00 fmp1 0 fmp0 0 6dh cier reset value wkuie 0 00 0 fovie0 0 ffie0 0 fmpie0 0 tmeie 0 6eh cdgr reset value 0 0 0 0 rx 1 samp 1 silm 0 lbkm 0 6fh cfpsr reset value 0 0 0 0 0 fps2 0 fps1 0 fps0 0 table 88. becan mailbox pages - register map and reset values address (hex.) register name 76543210 70h receive mfmi reset value fmi7 0 fmi6 0 fmi5 0 fmi4 0 fmi3 0 fmi2 0 fmi1 0 fmi0 0 70h tr a n s m i t mcsr reset value 0 0 terr 0 alst 0 txok 0 rqcp 0 abrq 0 txrq 0 71h mdlc reset value 0 xxxx dlc3 x dlc2 x dlc1 x dlc0 x 72h midr0 reset value x ide x rtr x stid10 x stid9 x stid8 x stid7 x stid6 x 73h midr1 reset value stid5 x stid4 x stid3 x stid2 x stid1 x stid0 x exid17 x exid16 x 74h midr2 reset value exid15 x exid14 x exid13 x exid12 x exid11 x exid10 x exid9 x exid8 x 75h midr3 reset value exid7 x exid6 x exid5 x exid4 x exid3 x exid2 x exid1 x exid0 x 76h:7dh mdar[0:7] reset value mdar7 x mdar6 x mdar5 x mdar4 x mdar3 x mdar2 x mdar1 x mdar0 x becan controller (becan) st72561-auto 258/324 doc id 12370 rev 8 7eh mtslr reset value time7 x time6 x time5 x time4 x time3 x time2 x time1 x time0 x 7fh mtshr reset value time15 x time14 x time13 x time12 x time11 x time10 x time9 x time8 x table 89. becan filter configuration page - register map and reset values address (hex.) register name 7 6 5 4 3 2 1 0 70h cesr reset value 0 lec2 0 lec1 0 lec0 00 boff 0 epvf 0 ewgf 0 71h ceier reset value errie 000 lecie 00 bofie 0 epvie 0 ewgie 0 72h tecr reset value tec7 0 tec6 0 tec5 0 tec4 0 tec3 0 tec2 0 tec1 0 tec0 0 73h recr reset value rec7 0 rec6 0 rec5 0 rec4 0 rec3 0 rec2 0 rec1 0 rec0 0 74h cbtr0 reset value sjw1 0 sjw0 0 brp5 0 brp4 0 brp3 0 brp2 0 brp1 0 brp0 0 75h cbtr1 reset value 0 bs22 0 bs21 1 bs20 0 bs13 0 bs12 0 bs11 1 bs10 1 76h reserved xxxxxxx x 77h reserved xxxxxxx x 78h cfmr0 reset value fmh3 0 fml3 0 fmh2 0 fml2 0 fmh1 0 fml1 0 fmh0 0 fml0 0 79h cfmr1 reset value 0000 fmh5 0 fml5 0 fmh4 0 fml4 0 7ah cfcr0 reset value ffa1 0 fsc11 0 fsc10 0 fact1 0 ffa0 0 fsc01 0 fsc00 0 fact0 0 7bh cfcr1 reset value ffa3 0 fsc31 0 fsc30 0 fact3 0 ffa2 0 fsc21 0 fsc20 0 fact2 0 7ch cfcr2 reset value ffa5 0 fsc51 0 fsc50 0 fact5 0 ffa4 0 fsc41 0 fsc40 0 fact4 0 table 88. becan mailbox pages - register map and reset values (continued) address (hex.) register name 76543210 st72561-auto 10-bit a/d converter (adc) doc id 12370 rev 8 259/324 18 10-bit a/d converter (adc) 18.1 introduction the on-chip analog to digital converter (adc) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 18.2 main features 10-bit conversion up to 16 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 117 . 18.3 functional description 18.3.1 digital a/d conversion result the conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dda (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low-level voltage reference) then the conversion result in the adcdrh an d adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conv ersion is stored in the adcdrh and adcdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and samp ling not being completed in the allotted time. 10-bit a/d converter (adc) st72561-auto 260/324 doc id 12370 rev 8 figure 117. adc block diagram 18.3.2 a/d conversion the analog input ports must be configured as input, no pull-up, no interrupt. refer to the chapter 8: i/o ports . using these pins as an alog inputs does not affe ct the ability of the port to be read as a logic input. in the adccsr register: select the cs[3:0] bits to assign the analog channel to convert. adc conversion mode: in the adccsr register: set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: the eoc bit is set by hardware. the result is in the adcdr registers. a read to the adcdrh resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll eoc bit 2. read the adcdrl register 3. read the adcdrh register. th is clears eoc automatically. to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read the adcdrh register. th is clears eoc automatically. ch2 ch1 eoc speed adon slow ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 4 f adc f cpu d1 d0 adcdrl 00 0 0 00 ch3 f cpu, f cpu /2 , f cpu /4 st72561-auto 10-bit a/d converter (adc) doc id 12370 rev 8 261/324 18.3.3 changing the conversion channel the application can change channels during conversion. when software modifies the ch[3:0] bits in the adccsr register, the cu rrent conversion is stopped, the eoc bit is cleared, and the a/d converter starts converting the newly selected channel. 18.3.4 adcdr consistency if an end of conversion event occurs after software has re ad the adcdrlsb but before it has read the adcdrmsb, there would be a risk that the two values read would belong to different samples. to guarantee consistency: the adcdrl and the adcdrh registers are locked when the adccrl is read the adcdrl and the adcdrh registers are unlocked when the adcdrh register is read or when adon is reset. this is important, as the adcdr register will not be updated until th e adcdrh register is read. 18.4 low power modes note: the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 18.5 interrupts none. 18.6 register description 18.6.1 control/status register (adccsr) read/ write (except bit 7 read only) reset value: 0000 0000 (00h) table 90. effect of low power modes on adc mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. 7 0 eoc speed adon slow ch3 ch2 ch1 ch0 10-bit a/d converter (adc) st72561-auto 262/324 doc id 12370 rev 8 bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by software reading the adcdrh register or writing to any bit of the adccsr register. 0: conversion is not complete 1: conversion complete bit 6 = speed a/d clock selection this bit is set and cleared by software. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: disable adc and stop conversion 1: enable adc and start conversion bit 4 = slow a/d clock selection this bit is set and cleared by software. it works together with the speed bit. refer to ta bl e 9 1 . bits 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. table 91. a/d clock selection f adc slow speed f cpu /2 0 0 f cpu (where f cpu <= 4 mhz) 1 f cpu /4 1 0 f cpu /2 (same frequency as slow = 0, speed = 0) 1 table 92. adc cha nnel selection channel pin (1) ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 1 ain2 1 0 ain3 1 ain4 1 0 0 ain5 1 ain6 1 0 ain7 1 st72561-auto 10-bit a/d converter (adc) doc id 12370 rev 8 263/324 18.6.2 data register (adcdrh) read only reset value: 0000 0000 (00h) bits 7:0 = d[9:2] msb of analog converted value 18.6.3 data register (adcdrl) read only 0000 0000 (00h) bits 7:2 = reserved. forced by hardware to 0. bits 1:0 = d[1:0] lsb of analog converted value ain8 1 0 0 0 ain9 1 ain10 1 0 ain11 1 ain12 1 0 0 ain13 1 ain14 1 0 ain15 1 1. the number of channels is device dependen t. refer to the devic e pinout description. table 92. adc channel selection (continued) channel pin (1) ch3 ch2 ch1 ch0 7 0 d9 d8 d7 d6 d5 d4 d3 d2 7 0 000000d1d0 table 93. adc register map and reset values address (hex.) register label 76543210 45h adccsr reset value eoc 0 speed 0 adon 0 slow 0 ch3 0 ch2 0 ch1 0 ch0 0 46h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 47h adcdrl reset value 0 0 0 0 0 0 0 0 0 0 0 0 d1 0 d0 0 instruction set st72561-auto 264/324 doc id 12370 rev 8 19 instruction set 19.1 cpu addressing modes the cpu features 17 different addressing mo des which can be classified in seven main groups: the cpu instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdivided in two submodes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 94. addressing mode groups addressing mode example inherent nop immediate ld a, #$55 direct ld a, $55 indexed ld a, ($55,x) indirect ld a, ([$55],x) relative jrne loop bit operation bset byte, #5 table 95. cpu addressing mode overview mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a, #$55 + 1 short direct ld a, $10 00..ff + 1 long direct ld a, $1000 0000..ffff + 2 no offset direct indexed ld a, (x) 00..ff + 0 short direct indexed ld a, ($10,x) 00..1fe + 1 long direct indexed ld a, ($1000,x) 0000..ffff + 2 short indirect ld a, [$10 ] 00..ff 00..ff byte + 2 long indirect ld a, [$10.w] 0000..ffff 00..ff word + 2 st72561-auto instruction set doc id 12370 rev 8 265/324 19.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. short indirect indexed ld a, ([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a, ([$10.w], x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10, #7 00..ff + 1 bit indirect bset [$10], #7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7, skip 00..ff + 2 bit indirect relative btjt [$10], #7, skip 00..ff 00..ff byte + 3 table 95. cpu addressing mode overview (continued) mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles instruction set st72561-auto 266/324 doc id 12370 rev 8 19.1.2 immediate immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. 19.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two submodes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff addressing space. direct (long) the address is a word, thus allowing 64 kbyte addressing space, but requires 2 bytes after the opcode. 19.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three submodes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte addressing space and requires 2 bytes after the opcode. 19.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations st72561-auto instruction set doc id 12370 rev 8 267/324 the pointer address follows the opcode. the indirect addressing mode consists of two submodes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. 19.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 96. instructions supporting direct, i ndexed, indirect and indirect indexed addressing (part 1) long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/substractions operations bcp bit compare table 97. instructions supporting direct, i ndexed, indirect and indirect indexed addressing (part 2) short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement instruction set st72561-auto 268/324 doc id 12370 rev 8 19.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two submodes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. 19.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrate d in the following table: bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine table 97. instructions supporting direct, i ndexed, indirect and indirect indexed addressing (part 2) (continued) short instructions only function available relative direct/i ndirect instructions function jrxx conditional jump callr call relative table 98. instruction groups description instruction load and transfer ld clr stack operation push pop rsp increment/ decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul st72561-auto instruction set doc id 12370 rev 8 269/324 19.2.1 using a prebyte the instructions are described with one to four opcodes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. ) shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf table 98. instruction groups description instruction memo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c instruction set st72561-auto 270/324 doc id 12370 rev 8 call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. int pin = 1 (ext. int pin high) jril jump if ext. int pin = 0 (ext. int pin low) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 memo description function/example dst src i1 h i0 n z c st72561-auto instruction set doc id 12370 rev 8 271/324 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z memo description function/example dst src i1 h i0 n z c electrical characteristics st72561-auto 272/324 doc id 12370 rev 8 20 electrical characteristics 20.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 20.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25c and t a =t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 20.1.2 typical values unless otherwise specified, typical data is based on t a =25c, v dd = 5v (for the 4.5v v dd 5.5v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 20.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 20.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 118 . figure 118. pin loading conditions 20.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 119 . c l st7 pin st72561-auto electrical characteristics doc id 12370 rev 8 273/324 figure 119. pin input voltage 20.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 20.2.1 voltage characteristics v in st7 pin symbol ratings maximum value unit v dd - v ss supply voltage 6.5 v v pp - v ss programming voltage 13 v in input voltage on any pin (1)(2) 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operatio n, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for reset , 10k for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st72561-auto 276/324 doc id 12370 rev 8 20.3.3 auxiliary voltage detector (avd) thresholds subject to general operating conditions for t a . figure 121. lvd startup behavior note: when the lvd is enabled, the mcu reaches its authorized operating voltage from a reset state. however, in some devices, the reset signal may be undefined until v dd is approximately 2v. as a consequence, the i/os may toggle when v dd is below this voltage. because flash write access is impossible below this voltage, the flash memory contents will not be corrupted. 20.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). symbol parameter conditions min typ max unit v it+(avd) 1 ? 0 avdf flag toggle threshold (v dd rise) 4.4 (1) 1. data based on characterization results, not tested in production. 4.6 4.9 v v it-(avd) 0 ? 1 avdf flag toggle threshold (v dd fall) 4.2 4.4 4.65 (1) v hys(avd) avd voltage threshold hysteresis v it+(avd) -v it-(avd) 250 mv v it- voltage drop between avd flag set and lvd reset activated v it-(avd) -v it-(lvd) 450 5v 2v v it+ lvd reset v d d t reset state in this area not defined st72561-auto electrical characteristics doc id 12370 rev 8 277/324 20.4.1 supply and clock managers the previous current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to obtain the total device consumption, the two current values must be added (except for halt mode). table 99. supply current consumption symbol parameter conditions flash devices rom devices unit typ (1) max (2) typ (1) max (2) i dd supply current in run mode (3) f osc = 2 mhz, f cpu =1 mhz f osc = 4 mhz, f cpu =2 mhz f osc = 8 mhz, f cpu =4 mhz f osc = 16 mhz, f cpu =8 mhz 1.8 3.2 6 10 3 5 8 15 1.1 2.2 4.4 8.9 2 3.5 6 12 ma supply current in slow mode (3) f osc = 2 mhz, f cpu = 62.5khz f osc = 4 mhz, f cpu = 125 khz f osc = 8 mhz, f cpu = 250 khz f osc = 16 mhz, f cpu = 500 khz 0.5 0.6 0.85 1.25 2.7 3 3.6 4 0.1 0.2 0.4 0.8 0.2 0.4 0.8 1.5 supply current in wait mode (3) f osc = 2 mhz, f cpu =1 mhz f osc = 4 mhz, f cpu =2 mhz f osc = 8 mhz, f cpu =4 mhz f osc = 16 mhz, f cpu =8 mhz 1 1.8 3.4 6.4 3 4 5 7 0.7 1.4 2.9 5.7 3 4 5 7 supply current in slow wait mode (2) f osc = 2 mhz, f cpu = 62.5 khz f osc = 4 mhz, f cpu = 125 khz f osc = 8 mhz, f cpu = 250 khz f osc = 16 mhz, f cpu = 500 khz 0.4 0.5 0.6 0.8 1.2 1.3 1.8 2 0.07 0.14 0.28 0.56 0.12 0.2 0.5 1 supply current in halt mode (4) v dd =5.5v -40c t a +85c <1 10 <1 10 a -40c t a +125c 50 50 supply current in active halt mode (4)(5) 0.5 1.2 0.18 0.25 ma supply current in awufh mode (4)(5) v dd = 5.5v -40c t a +85c 25 30 25 30 a -40c t a +125c 70 70 1. typical data are based on t a = 25c, v dd =5v (4.5v v dd 5.5v range). 2. data based on characterization results, tested in production at v dd max., f cpu max. and t a max. 3. measurements are done in the following conditions: - program executed from flash, cpu r unning with flash (f or flash devices). - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state. - clock input (osc1) driven by external square wave. - in slow and slow wait mode, f cpu is based on f osc divided by 32. to obtain the total current consumption of the device, add the clock source ( section 20.5.1: crystal and ceramic resonator oscillators ) and the peripheral power consumption ( section 20.4.2: on-chip peripherals ). 4. all i/o pins in input mode with a static value at v dd or v ss (no load). data based on characterization results, tested in production at v dd max., f cpu max. and t a max. 5. this consumption refers to the halt period only an d not the associated run period which is software dependent. electrical characteristics st72561-auto 278/324 doc id 12370 rev 8 20.4.2 on-chip peripherals t a = 25c, f cpu =8 mhz . table 100. clock source current consumption symbol parameter conditions typ max (1) 1. data based on characterization results, not tested in production. unit i dd(res) supply current of resonator oscillator (2)(3) 2. data based on characterization results done with the external components specified in section 20.5.1: crystal and ceramic resonator oscillators , not tested in production. 3. as the oscillator is based on a current source, the cons umption does not depend on the voltage. see section 20.5.1: crystal and ceramic resonator oscillators a i dd(pll) pll supply current v dd = 5v 360 i dd(lvd) lvd supply current halt mode, v dd = 5v 150 300 table 101. peripheral consumption symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current (1) 1. data based on a differential i dd measurement between reset configur ation (timer counter running at f cpu /4) and timer counter stopped (only timd bit set). data valid for one timer. v dd = 5.0v 50 a i dd(tim8) 8-bit timer supply current (1) i dd(art) art pwm supply current (2) 2. data based on a differential i dd measurement between reset confi guration (timer stopped) and timer counter enabled (only tce bit set). 75 i dd(spi) spi supply current (3) 3. data based on a differential i dd measurement between reset configurat ion (spi disabled) and a permanent spi master communication at maximum speed (data sent equal to 55h).this me asurement includes the pad toggling consumption. 400 i dd(sci) sci supply current (4) 4. data based on a differential i dd measurement between sci low power state (scid = 1) and a permanent sci data transmit sequence. data valid for one sci. i dd(adc) adc supply current when converting (5) 5. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. i dd(can) can supply current (6) 6. data based on a differential i dd measurement between reset configuration (can disabled) and a permanent can data transmit sequence with rx and tx connected together. this measurement include the pad toggling consumption. 800 st72561-auto electrical characteristics doc id 12370 rev 8 279/324 20.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . figure 122. typical application with an external clock source table 102. general timings symbol parameter conditions min typ (1) 1. data based on typical application software. max unit t c(inst) instruction cycle time 2312t cpu f cpu = 8 mhz 250 375 1500 ns t v(it) interrupt reaction time (2) t v(it) = t c(inst) + 10 2. time measured between interrupt event and interrupt vector fetch. d t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 10 22 t cpu f cpu = 8 mhz 1.25 2.75 s table 103. external clock source symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 122 0.7 x v dd -v dd v v osc1l osc1 input pin low level voltage v ss -0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time (1) 1. data based on design simulation and/or technology characteristics, not tested in production. 25 - ns t r(osc1) t f(osc1) osc1 rise or fall time (1) -5 i l oscx input leakage current v ss v in v dd -1a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10% electrical characteristics st72561-auto 280/324 doc id 12370 rev 8 20.5.1 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ ceramic resonator oscillators. all the information given in this pa ragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to t he crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...) (a)(b) . figure 123. typical application with a crystal or ceramic resonator a. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. b. t su(osc) is the typical oscillator st art-up time measured between v dd = 2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (< 50 s). table 104. oscillator characteristics symbol parameter conditions min max unit f osc oscillator frequency (1) 1. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value. refer to crystal/ceramic re sonator manufacturer for more details. lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 1 >2 >4 >8 2 4 8 16 mhz r f feedback resistor 20 40 k c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) r s =200 lp oscillator r s =200 mp oscillator r s =200 ms oscillator r s =100 hs oscillator 22 22 18 15 56 46 33 33 pf i 2 osc2 driving current v dd = 5v lp oscillator v in =v ss mp oscillator ms oscillator hs oscillator 80 160 310 610 150 250 460 910 a osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors st72561-auto electrical characteristics doc id 12370 rev 8 281/324 20.5.2 pll characteristics operating conditions: v dd 3.8 to 5.5v @ t a 0 to 70c (a) or v dd 4.5 to 5.5v @ t a -40 to 125c figure 124. pll jitter vs signal frequency (1) 1. measurement conditions: f cpu = 4 mhz, t a = 25c the user must take the pll jitter into account in the application (for example in serial communication or sampling of high frequency signals). the pll jitter is a periodic effect, which is integrated over several cpu cycles. therefore, the longer the period of the application signal, the less it is impacted by the pll jitter. figure 124 shows the pll jitter integrated on application signals in the range 125 khz to 2 mhz. at frequencies of less than 125 khz, the jitter is negligible. a. data characterized but not tested table 105. pll characteristics symbol parameter conditions min typ max unit v dd(pll) pll voltage range t a = 0 to +70 c 3.8 5.5 t a = -40 to +125 c4.5 f osc pll input frequency range 24mhz f cpu /f cpu pll jitter (1) 1. data characterized but not tested. f osc = 4 mhz, v dd = 4.5 to 5.5v see note (2) 2. under characterization. % f osc = 2 mhz, v dd = 4.5 to 5.5v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2000 1000 500 250 125 application signal frequency (khz) +/-jitter (%) pll on pll off electrical characteristics st72561-auto 282/324 doc id 12370 rev 8 20.6 auto wakeup from halt oscillator (awu) figure 125. awu oscillator freq. @ t a 25c 20.7 memory characteristics 20.7.1 ram and hardware registers 20.7.2 flash memory table 106. awu oscillator characteristics symbol parameter conditions min typ max unit f awu awu oscillator frequency (1) 1. data based on characterization results, not tested in production. 50 100 250 khz t rcsrt awu oscillator startup time 10 s 4.4 5 5.6 vdd 50 100 150 200 freq(khz) ta=25c table 107. ram supply voltage symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware register s (only in halt mode). not tested in production. halt mode (or reset) 1.6 - - v table 108. dual voltage hdflash memory symbol parameter conditions min (1) typ max (1) unit f cpu operating frequency read mode 0 8 mhz write / erase mode 1 8 v pp programming voltage (2) 4.5v v dd 5.5v 11.4 12.6 v i pp v pp current (3)(4) read (v pp = 12v) 200 a write / erase 30 ma t vpp internal v pp stabilization time 10 (3) s st72561-auto electrical characteristics doc id 12370 rev 8 283/324 20.8 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 20.8.1 functional ems (elect romagnetic susceptibility) based on a simple running application on the product (toggling two leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials: t ret data retention t a =55c 20 years n rw write erase cycles t a = 85c 100 cycles t prog t erase programming or erasing temperature range -40 25 85 c 1. data based on characterization results, not tested in production. 2. v pp must be applied only during the programming or eras ing operation and not permanently for reliability reasons. 3. data based on simulation results, not tested in production. 4. in write / erase mode the idd supply current consumption is the same as in run mode (see section 20.2.2 ) table 108. dual voltage hdflash memory (continued) symbol parameter conditions min (1) typ max (1) unit electrical characteristics st72561-auto 284/324 doc id 12370 rev 8 most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). 20.8.2 electromagnetic interference (emi) based on a simple application running on the product (toggling two leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the boar d and the loading of each pin. 20.8.3 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity (see ta b l e 1 1 1 and ta b l e 1 1 2 below). for more details, refer to application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size table 109. ems test results symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8 mhz conforms to iec 1000-4-2 3b v fftb fast transient voltage burst limits to be applied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8 mhz conforms to iec 1000-4-4 table 110. emi emissions symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] (1) unit 8/4 mhz 16/8 mhz s emi peak level flash devices: v dd = 5v, t a = +25c, lqfp64 package conforming to sae j 1752/3 0.1 mhz to 30 mhz 31 32 dbv 30 mhz to 130 mhz 32 37 130 mhz to 1 ghz 11 16 sae emi level 3.0 3.5 - rom devices: v dd = 5v, t a = +25c, lqfp64 package conforming to sae j 1752/3 0.1 mhz to 30 mhz 10 18 dbv 30 mhz to 130 mhz 15 25 130 mhz to 1 ghz -3 1 sae emi level 2.0 2.5 - 1. not tested in production. st72561-auto electrical characteristics doc id 12370 rev 8 285/324 depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. static and dynamic latch-up lu : three complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to application note an1181. dlu : electrostatic discharges (one positive then one negative test) are applied to each pin of three samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the mi cro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards. for more details, refer to application note an1181. table 111. absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25c 2000 v v esd(mm) electrostatic discharge voltage (machine model) 200 v esd(cdm) electro-tatic discharge voltage (charge device model) 750 on corner pins, 500 on others table 112. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latch-up class t a = +25c t a = +85c t a = +125c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c electrical characteristics st72561-auto 286/324 doc id 12370 rev 8 20.9 i/o port pin characteristics 20.9.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. table 113. i/o characteristics symbol parameter conditions min typ max unit v il input low level voltage (1) cmos ports 0.3 x v dd v v ih input high level voltage (1) 0.7 x v dd v hys schmitt trigger voltage hysteresis (2) 1 v il input low level voltage (1) ttl ports 0.8 v ih input high level voltage (1) 2 v hys schmitt trigger voltage hysteresis (2) 400 mv i inj(pin) injected current on pb3 v dd =5v flash devices 0 +4 ma rom devices 4 injected current on any other i/o pin 4 i inj(pin) (3) total injected current (sum of all i/o and control pins) (4) 25 i lkg input leakage current on robust pins see section 20.13: 10-bit adc characteristics input leakage current (5) v ss v in v dd 1 a i s static current consumption (6) floating input mode 200 r pu weak pull-up equivalent resistor (7) v in = v s s v dd = 5v 50 90 250 k c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time c l = 50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time t w(it)in external interrupt pulse time (4) 1t cpu 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switchin g levels. based on characterization results, not tested. 3. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative inject ion is induced by v in electrical characteristics st72561-auto 288/324 doc id 12370 rev 8 20.9.2 output driving current subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 129. typical v ol at v dd = 5v (standard) figure 130. typical v ol at v dd = 5v (high-sink) table 114. output driving current symbol parameter conditions min max unit v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in section 20.2.2: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for a standard i/o pin when eight pins are sunk at same time (see figure 129 ) v dd = 5 v i io =+5ma 1.2 v i io =+2ma 0.5 output low level voltage for a high sink i/o pin when four pins are sunk at same time (see figure 130 and figure 133 ) i io =+20ma, t a 85 c t a 85 c 1.3 1.5 i io = +8 ma 0.6 v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in section 20.2.2: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . output high level voltage for an i/o pin when four pins are sourced at same time (see figure 131 and figure 134 ) i io =-5ma, t a 85 c t a 85 c v dd -1.4 v dd -1.6 i io =-2ma v dd -0.7 25 iio(ma) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 voh(v) -45c 25c 130c 25 820 iol (ma) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 vol (v) -45c 25c 130c st72561-auto electrical characteristics doc id 12370 rev 8 289/324 figure 131. typical v oh at v dd =5v figure 132. typical v ol vs v dd (standard i/os) figure 133. typical v ol vs v dd (high-sink i/os) -2 -5 iio(ma) 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 voh(v) -45c 25c 130c 3456 vdd(v) 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 vol(v) iio=5ma -45c 25c 130c 3456 vdd(v) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 vol(v) iio=2ma -45c 25c 130c 3456 vdd(v) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 vol(v) iio=8ma -45c 25c 130c 3456 vdd(v) 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 vol(v) iio=20ma -45c 25c 130c electrical characteristics st72561-auto 290/324 doc id 12370 rev 8 figure 134. typical v oh vs v dd 20.10 control pin characteristics 20.10.1 asynchronous reset pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. 3456 vdd(v) 2 3 4 5 6 voh(v) iio=2ma -45c 25c 130c 3456 vdd(v) 1 2 3 4 5 6 voh(v) iio=5ma -45c 25c 130c table 115. reset pin characteristics symbol parameter conditions min typ max unit v il input low level voltage (1) 0.3 x v dd v v ih input high level voltage (1) 0.7 x v dd v hys schmitt trigger voltage hysteresis (2) v dd =5v 1.5 v ol output low level voltage (3) v dd =5v i io = +5ma 0.68 0.95 i io = +2ma 0.28 0.45 r on weak pull-up equivalent resistor (4) v in = v ss 20 40 80 k t w(rstl)out generated reset pulse duration internal reset source 30 s t h(rstl)in external reset pulse hold time (5) 2.5 t g(rstl)in filtered glitch duration (6) 200 ns 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switching levels. 3. the i io current sunk must always respect th e absolute maximum rating specified in section 20.2.2: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vss . 4. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on the reset pin with a duration below t h(rstl)in can be ignored. 5. the reset network (the resistor and two capacitors) protec ts the device against parasitic resets, especially in noisy environments. 6. data guaranteed by design, not tested in production. st72561-auto electrical characteristics doc id 12370 rev 8 291/324 reset circuit design recommendations the reset network protects the device against parasitic resets. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 20.10.1: asynchronous reset pin . otherwise the reset will not be taken into account internally. because the reset circui t is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-up for example) is less than the absol ute maximum value specified for i inj(reset) in section 20.2.2: current characteristics . reset pin protection when lvd is disabled figure 135. reset pin protection when lvd is disabled reset pin protection when lvd is enabled figure 136. reset pin protection when lvd is enabled note: when the lvd is enabled, it is mandatory not to connect a pull-up resistor. a 10nf pull-down capacitor is recommended to filter noise on the reset line. in case a capacitive power supply is used, it is recommended to connect a 1 m pull-down resistor to the reset pin to discharge any resi dual voltage induced by this capacitive power supply (this will add 5 a to th e power consumption of the mcu). 0.01f external reset circuit user v dd 4.7k required st72xxx pulse generator filter r on v dd watchdog internal reset 0.01f st72xxx pulse generator filter r on v dd watchdog lvd reset internal reset reset external recommended 1m optional (see note ) electrical characteristics st72561-auto 292/324 doc id 12370 rev 8 tips when using the lvd 1. check that all recommendations related to reset circuit have been applied (see reset circuit design recommendations ) 2. check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709. if this cannot be done, it is recommended to put a 100 nf + 1m pull- down on the reset pin. 3. the capacitors connected on the reset pin and also the power supply are key to avoiding any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. othe rwise: replace 10nf pull-down on the reset pin with a 5 f to 20 f capacitor. figure 137. reset r pu vs v dd 20.10.2 iccsel/ v pp pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 138. two typical applications with iccsel/v pp pin 1. when icc mode is not required by the application iccsel/v pp pin must be tied to v ss . 3.5 4 4.5 5 5.5 vdd 0 20 40 60 80 100 rpu (kohm) ta=-45c ta=25c ta=130c table 116. iccsel/v pp pin characteristics symbol parameter conditions min max unit v il input low level voltage (1) 1. data based on design simulation and/or technology characteristics, not tested in production. v ss 0.2 v v ih input high level voltage (1) v dd -0.1 12.6 i l input leakage current v in =v ss 1 a iccsel/v pp st72xxx 10k programming tool v pp st72xxx st72561-auto electrical characteristics doc id 12370 rev 8 293/324 20.11 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). table 117. 8-bit pwm-art auto reload timer characteristics symbol parameter conditions min typ max unit t res(pwm) pwm resolution time 1t cpu f cpu = 8 mhz 125 ns f ext art external clock frequency 0f cpu /2 mhz f pwm pwm repetition rate res pwm pwm resolution 8 bit v os pwm/dac output step voltage v dd =5v, res=8- bits 20 mv t counter timer clock period when internal clock is selected f cpu =8 mhz 1 128 t cpu 0.125 16 s table 118. 8-bit timer characteristics symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2 f cpu = 8 mhz 250 ns f pwm pwm repetition rate 0 f cpu /4 mhz res pwm pwm resolution 8 bit t counter timer clock period f cpu =8 mhz 2 8000 t cpu 0.250 1000 s table 119. 16-bit timer characteristics symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2 f cpu = 8 mhz 250 ns f ext timer external clock frequency 0f cpu /4 mhz f pwm pwm repetition rate res pwm pwm resolution 16 bit electrical characteristics st72561-auto 294/324 doc id 12370 rev 8 t counter timer clock period when internal clock is selected f cpu =8 mhz 28t cpu 0.250 1 s table 119. 16-bit timer characteristics (continued) symbol parameter conditions min typ max unit st72561-auto electrical characteristics doc id 12370 rev 8 295/324 20.12 communication interface characteristics 20.12.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). table 120. spi characteristics symbol parameter conditions min max unit f sck =1/t c(sck) spi clock frequency master, f cpu = 8 mhz f cpu / 128 = 0.0625 f cpu /4=2 mhz slave, f cpu =8 mhz 0 f cpu /2=4 t r(sck) spi clock rise and fall time see i/o port pin description t f(sck) t su(ss ) (1) ss setup time (2) slave (4 x t cpu )+50 ns t h(ss ) (1) ss hold time 120 t w(sckh) (1) sck high and low time master 100 t w(sckl) (1) slave 90 t su(mi) (1) data input setup time master 100 t su(si) (1) slave t h(mi) (1) data input hold time master t h(si) (1) slave t a(so) (1) data output access time slave 0 120 t dis(so) (1) data output disable time 240 t v(so) (1) data output valid time slave (after enable edge) 90 t h(so) (1) data output hold time 0 t v(mo) (1) data output valid time master (after enable edge) 120 t h(mo) (1) data output hold time 0 1. data based on design simulation and/or char acterization results, not tested in production. 2. depends on f cpu . for example, if f cpu = 8 mhz, then t cpu =1/f cpu = 125ns and t su(ss ) = 550ns. electrical characteristics st72561-auto 296/324 doc id 12370 rev 8 figure 139. spi slave timing diagram with cpha = 0 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, t he pin status depends on the i/o port configuration. figure 140. spi slave timing diagram with cpha = 1 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, t he pin status depends on the i/o port configuration. ss input sck input cpha = 0 mosi input miso output cpha = 0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out see note 2 cpol = 0 cpol = 1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in ss input sck input cpha = 1 mosi input miso output cpha = 1 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol = 0 cpol = 1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in st72561-auto electrical characteristics doc id 12370 rev 8 297/324 figure 141. spi master timing diagram 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, t he pin status depends on the i/o port configuration. 20.12.2 can - controller area network interface subject to general operating condition for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (cantx and canrx). 20.13 10-bit adc characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. ss input sck input cpha = 0 mosi output miso input cpha = 0 cpha = 1 cpha = 1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 see note 2 cpol = 0 cpol = 1 cpol = 0 cpol = 1 t r(sck) t f(sck) t h(mo) t v(mo) table 121. can characteristics symbol parameter conditions min typ max unit t p(rx:tx) can controller propagation time (1) 1. data based on characterization results, not tested in production. - - 60 ns table 122. adc characteristics symbol parameter conditions min (1) typ max (1) unit f adc adc clock frequency 0.4 4 mhz v ain conversion voltage range (2) v ssa v dda v electrical characteristics st72561-auto 298/324 doc id 12370 rev 8 figure 142. r ain max vs f adc with c ain = 0pf 1. c parasitic represents the capacitance of the pcb ( dependent on soldering and pcb layout quality) plus the pad capacitance (3pf). a high c parasitic value will downgrade conversi on accuracy. to remedy this, f adc should be reduced. 2. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k ). data based on characterization re sults, not tested in production. r ain external input impedance see figure 142 and figure 143 k c ain external capacitor on analog input pf f ain variation frequency of analog input signal hz i lkg negative input leakage current on robust analog pins (refer to ta bl e 3 ) v in < v ss , | i in | < 400a on adjacent robust analog pin 56 a c adc internal sample and hold capacitor 6pf t conv conversion time f adc =4 mhz 3.5 s 14 1/f adc i adc analog part sunk on v dda 2) 3.6 ma digital part sunk on v dd 0.2 1. data based on characterization results, not tested in production. 2. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss . table 122. adc characteristics (continued) symbol parameter conditions min (1) typ max (1) unit 0 5 10 15 20 25 30 35 40 45 0103070 c parasitic (pf) max. r ain (kohm) 4 mhz 2 mhz 1 mhz st72561-auto electrical characteristics doc id 12370 rev 8 299/324 figure 143. recommended c ain /r ain values 1. figure 143 shows that depending on the input signal variation (f ain ), c ain can be increased for stabilization time and reduced to allow the use of a larger serial resistor (r ain) . it is valid for all f adc frequencies 4mhz. figure 144. typical application with adc analog power supply and reference pins depending on the mcu pin count, the package may feature separate v dda and v ssa analog power supply pins. these pins supply power to the a/d converter cell and function as the high and low reference voltages for the conversion. in smaller packages v dda and v ssa pins are not available and the analog supply and reference pads are internally bonded to the v dd and v ss pins. separation of the digital and analog power pins allow board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see general pcb design guidelines ). general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. use separate digital and analog planes. the analog ground plane should be connected to the digital ground plane via a single point on the pcb. filter power to the analog power planes. it is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1 1 10 100 1000 0.01 0.1 1 10 f ain (khz) max. r ain (kohm) cain 10 nf cain 22 nf cain 47 nf ainx st72xxx v dd i l 1a v t 0.6v v t 0.6v c adc 6pf v ain r ain 10-bit a/d conversion 2k ( max ) c ain electrical characteristics st72561-auto 300/324 doc id 12370 rev 8 0.1f and optionally, if needed 10pf capacitors as close as possible to the st7 power supply pins and a 1 to 10f capacitor close to the power source (see figure 145 ). the analog and digital power supplies should be connected in a star network. do not use a resistor, as v dda is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital outputs on the same i/o port as the a/d input being converted. software filtering of spurious conversion results for emc performance reasons, it is recommended to filter a/d conversion outliers using software filtering techniques. figure 145. power supply filtering adc accuracy table 123. adc accuracy with f cpu = 8 mhz, f adc = 4 mhz r ain < 10kw, v dd = 5v symbol parameter co nditions typ max unit |e t | total unadjusted error (1) 1. data based on characterization results, not tested in production. adc accuracy vs. negative injection current: injecting negative current on any of the st andard (non-robust) analog i nput pins should be avoided as this significantly reduces the accuracy of t he conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. the effect of negative injecti on current on robust pins is specified in section 20.9: i/o port pin characteristics . any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 20.9: i/o port pin characteristics does not affect the adc accuracy 4note (2) 2. under characterization. lsb |e o | offset error (1) 2.5 4 |e g | gain error (1) 3 |e d | differential linearity error (1) 1.5 2 |e l | integral linearity error (1) v ss v dd 0.1f v dd st72xxx v dda v ssa power supply source st7 digital noise filtering external noise filtering 1 to 10f 0.1f st72561-auto electrical characteristics doc id 12370 rev 8 301/324 figure 146. adc accuracy e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = v in (lsbideal) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line et=total unadjusted error: maximum deviation between the actual and the ideal transfer curves. eo=offset error: deviation between the first actual transition and the first ideal one. eg=gain error: deviation between the last ideal transition and the last actual one. ed=differential linearity error: maximum deviation between actual steps and the ideal one. el=integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dda v ssa package characteristics st72561-auto 302/324 doc id 12370 rev 8 21 package characteristics 21.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 21.2 package mechanical data figure 147. 64-pin low profile quad flat package (14x14) dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.80 0.031 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n64 c h l l1 e b a a1 a2 e e1 d d1 st72561-auto package characteristics doc id 12370 rev 8 303/324 figure 148. 32-pin low profile quad flat package (7x7) figure 149. 44-pin low profile quad flat package (10x10) dim. mm inches (1) 1. values in inches are converted from mm and rounded to 3 decimal digits. min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 9.00 0.354 d1 7.00 0.276 e 9.00 0.354 e1 7.00 0.276 e 0.80 0.031 q 03.57 0 3.57 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n32 h c l l1 b e a1 a2 a e e1 d d1 dim. mm inches (1) 1. values in inches are converted from mm and rounded to 3 decimal digits. min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.000 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.80 0.031 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n44 a a2 a1 b e l1 l h c e e1 d d1 package characteristics st72561-auto 304/324 doc id 12370 rev 8 figure 150. 64-pin low profile quad flat package (10 x10) 21.3 thermal characteristics 21.4 packaging for automatic handling the devices can be supplied in trays or with tape and reel conditioning. tape and reel conditioning can be ordered with pin 1 left-oriented or right-oriented when facing the tape sprocket holes as shown in figure 151 . dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.50 0.020 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n64 a a2 a1 c l1 l e e1 d d1 e b symbol ratings value unit r thja package thermal resistance (junction to ambient) lqfp64 lqfp44 lqfp32 60 52 70 c/w p d power dissipation (1) 1. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation depe nding on the ports used in the application. 500 mw t jmax maximum junction temperature (2) 2. the maximum chip-junction temperature is based on technology characteristics. 150 c st72561-auto package characteristics doc id 12370 rev 8 305/324 figure 151. pin 1 orientation in tape and reel conditioning see also figure 152: st72f561xx-auto flash commercial product structure on page 310 and figure 153: st72p561xxx-auto fastrom commercial product structure on page 311 . right orientation (eia 481-c compliant) left orientation pin 1 pin 1 device configuration and ordering information st72561-auto 306/324 doc id 12370 rev 8 22 device configuration and ordering information 22.1 introduction each device is available for production in user programmable versions (flash) as well as in factory coded versions (rom/fastrom). st72561-auto devices are rom versions. st72p561-auto devices are factory advanced service technique rom (fastrom) versions: they are factory-programmed hdflash devices. st72f561-auto flash devices are shipped to customers with a default content (ffh), while rom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer using the option bytes while the rom devices are factory-configured. 22.2 flash devices 22.2.1 flash configuration the option bytes allows the hardware configuration of the microcontroller to be selected. they have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 programming tool). the default content of the flash is fixed to ffh. to program directly the flash devices using icp, flash devices are shipped to customers with a reserved internal clock source enabled. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). option byte 0 opt7 = wdghalt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode opt6 = wdgsw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt5 = reserved, must be kept at default value. opt4 = lv d voltage detection this option bit enables the voltage detection block (lvd). 0: lvd on 1: lvd off opt3 = pll off pll activation this option bit activates the pll which allows multiplication by two of the main input clock frequency. the pll is guaranteed only with an input frequency between 2 and 4 mhz. 0: pll x2 enabled 1: pll x2 disabled st72561-auto device configuration and ordering information doc id 12370 rev 8 307/324 caution: the pll can be enabled only if the ?osc range? (opt11:10) bits are configured to ?mp - 2~4 mhz?. otherwise, the device functionality is not guaranteed. opt2:1 = pkg[1:0] package selection these option bits select the device package. note: pads that are not bonded to external pins are in input pull-up configuration when the package selection option bits have been properly programmed. the configuration of these pads must be kept in reset state to avoid added current consumption. opt0 = fmp_r flash memory read-out protection read-out protection, when selected provides a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is selected causes the whole user memory to be erased first, and the device can be reprogrammed. refer to section 3.3.1: read-out protection and the st7 flash programming reference manual for more details. 0: read-out protection enabled 1: read-out protection disabled option byte 1 opt7:6 = afi_map[1:0] afi mapping these option bits allow the mapping of some of the alternate functions to be changed. static option byte 0 s tatic option byte 1 707 0 wdg reserved lv d plloff pkg fmp_r afi_map osctype oscrange reserved rstc halt sw 10 1 0 1 0 1 0 default (1) 1. option bit values programmed by st. 111111111 1 1 0 1 1 11 table 124. package selection selected package pkg 10 lqfp 64 1 x lqfp 44 0 1 lqfp 32 0 device configuration and ordering information st72561-auto 308/324 doc id 12370 rev 8 opt5:4 = osctype[1:0] oscillator type these option bits select the st7 main clock source type. opt3:2 = oscrange[1:0] oscillator range if the resonator oscillator type is selected, these option bits select the resonator oscillator. this selection corresponds to the frequency range of the resonator used. if external source is selected with the osctype option, then the oscrange option must be selected with the corresponding range. table 125. alternate function remapping 1 afi mapping 1 afi_map(1) t16_ocmp1 on pd3 t16_ocmp2 on pd5 t16_icap1 on pd4 linsci2_sck not available linsci2_tdo not available linsci2_rdi not available 0 t16_ocmp1 on pb6 t16_ocmp2 on pb7 t16_icap1 on pc0 linsci2_sck on pd3 linsci2_tdo on pd5 linsci2_rdi on pd4 1 table 126. alternate function remapping 0 afi mapping 0 afi_map(0) t16_icap2 is mapped on pd1 0 t16_icap2 is mapped on pc1 1 table 127. osctype selection clock source osctype 10 resonator oscillator 0 0 reserved 1 reserved internal clock source (used only in icc mode) 1 0 external source 1 table 128. oscrange selection typical frequency range oscrange 10 lp 1~2 mhz 0 0 mp 2~4 mhz 1 st72561-auto device configuration and ordering information doc id 12370 rev 8 309/324 opt1 = reserved opt0 = rstc reset clock cycle selection this option bit selects the number of cpu cy cles inserted during the reset phase and when exiting halt mode. for resonator oscillato rs, it is advised to select 4096 due to the long crystal stabilization time. 0: reset phase with 4096 cpu cycles 1: reset phase with 256 cpu cycles ms 4~8 mhz 1 0 hs 8~16 mhz 1 table 128. oscrange selection (continued) typical frequency range oscrange 10 device configuration and ordering information st72561-auto 310/324 doc id 12370 rev 8 22.2.2 flash ordering information the following figure 152 serves as a guide for ordering. figure 152. st72f561xx-auto flash commercial product structure 1. for a list of available options (e.g. memory size, package) and or derable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. st72 f 561 k 6 t a x s product class st72 microcontroller pin count k = 32 pins j = 44 pins ar = 64 pins 10 x 10 mm r = 64 pins 14 x 14 mm package type t = lqfp example: sub-family type 561 = 561 sub-family family type f = flash temperature range a = -40 c to 85 c c = -40 c to 125 c program memory size 4 = 16 kbytes 6 = 32 kbytes 7 = 48 kbytes 9 = 60 kbytes tape and reel conditioning options (left blank if tray) tr or r = pin 1 left-oriented tx or x = pin 1 right-oriented (eia 481-c compliant) ecopack/fab code blank or e = lead-free ecopack ? phoenix fab s = lead-free ecopack ? catania fab st72561-auto device configuration and ordering information doc id 12370 rev 8 311/324 22.3 transfer of customer code customer code is made up of the rom/fastrom contents and the list of the selected options (if any). the rom/fastrom contents are to be sent on diskette, or by electronic means, with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization is pleased to provide detailed information on contractual points. the following figure 153 serves as a guide for ordering. figure 153. st72p561xxx-auto fastrom commercial product structure st72 p 561 t a /xxx x s product class st72 microcontroller package type t = lqfp example: sub-family type 561 = 561 sub-family family type p = fastrom temperature range a = -40 c to 85 c c = -40 c to 125 c tape and reel conditioning options (left blank if tray) tr or r = pin 1 left-oriented tx or x = pin 1 right-oriented (eia 481-c compliant) ecopack/fab code blank or e = lead-free ecopack ? phoenix fab s = lead-free ecopack ? catania fab code name defined by stmicroelectronics. denotes rom code, pinout and program memory size. device configuration and ordering information st72561-auto 312/324 doc id 12370 rev 8 figure 154. st72561xx-auto rom commercial product structure st72 561 t a /xxx x s product class st72 microcontroller package type t = lqfp example: sub-family type 561 = 561 sub-family temperature range a = -40 c to 85 c c = -40 c to 125 c tape and reel conditioning options (left blank if tray) tr or r = pin 1 left-oriented tx or x = pin 1 right-oriented (eia 481-c compliant) ecopack/fab code blank or e = lead-free ecopack ? phoenix fab s = lead-free ecopack ? catania fab code name defined by stmicroelectronics. denotes rom code, pinout and program memory size. st72561-auto device configuration and ordering information doc id 12370 rev 8 313/324 st72561-auto microcontroller option list (last update: march 2008) customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . * the rom/fastrom code name is assigned by stmicroelectronics. rom/fastrom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/package (check only one option) conditioning: [ ] tray [ ] tape & reel special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ " (lqfp32 7 characters, other packages 10 characters max.) authorized characters are letters, digits, '.', '-', '/' and spaces only. temperature range: [ ] a (-40c to +85c) [ ] c (-40c to +125c) clock source selection: [ ] resonator [ ] external source oscillator/external source range: [ ] lp: low power (1 to 2 mhz) [ ] mp: medium power (2 to 4 mhz) [ ] ms: medium speed (4 to 8 mhz) [ ] hs: high speed (8 to 16 mhz) lvd [ ] disabled [ ] enabled pll1 [ ] disabled [ ] enabled watchdog selection [ ] software activation [ ] hardware activation watchdog reset on halt [ ] reset [ ] no reset read-out protection [ ] disabled [ ] enabled reset delay [ ] 256 cycles [ ] 4096 cycles linsci2 mapping [ ] not available (afimap[ 1] = 0) [ ] mapped (afimap[1] = 1) t16_icap2 mapping [ ] on pd1 (afimap[0] = 0) [ ] on pc1 (afimap[0] = 1) comments: supply operating range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 if pll is enabled, medium power (2 to 4 mhz range) has to be selected (mp) 2 lqfp64 14x14 available only in automotive version. please download the latest version of this option list from: www.st.com rom: | | ---------------------- package ----------------------- | | ------------------------- 60k ------------------------- | | ------------------------- 48k ------------------------- | | ------------------------ 32k ------------------------ | | ------------------------ 16k ------------------------ | | |lqfp64 10x10: |[ ] st72561ar9 |[ ] st72561ar7 |[ ] st72561ar6 |[ ] st72561ar4 | |lqfp64 14x14: 2 |[ ] st72561r9 |[ ] st72561r7 |[ ] st72561r6 |[ ] st72561r4 | |lqfp44: |[ ] st72561j9 |[ ] st72561j7 |[ ] st72561j6 |[ ] st72561j4 | |lqfp32: |[ ] st72561k9 |[ ] st72561k7 |[ ] st72561k6 |[ ] st72561k4 | fastrom: | | ----------------------- package ----------------------- | | ------------------------- 60k ------------------------- | | ------------------------- 48k ------------------------- | | ------------------------ 32k ------------------------ | | ------------------------ 16k16k ------------------------ | | |lqfp64 10x10: |[ ] st72p561ar9 |[ ] st72p561ar7 |[ ] st72p561ar6 |[ ] st72p561ar4 | |lqfp64 14x14: 2 |[ ] st72p561r9 |[ ] st72p561r7 |[ ] st72p561r6 |[ ] st72p561r4 | |lqfp44: |[ ] st72p561j9 |[ ] st72p561j7 |[ ] st72p561j6 |[ ] st72p561j4 | |lqfp32: |[ ] st72p561k9 |[ ] st72p561k7 |[ ] st72p561k6 |[ ] st72p561k4 | development tools st72561-auto 314/324 doc id 12370 rev 8 23 development tools full details of tools available for the st7 from third party manufacturers can be obtained from the stmicroelectronics internet site: www.st.com . tools from isystem and hitex include c compliers, emulators and gang programmers. note: before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device. for footprint and other mechanical information about these sockets and adapters, refer to the manufacturer?s datasheet. st programming tools st7mdt25-epb: for in-socke t or icc programming st7-stick: for icc programming st72561-auto important notes doc id 12370 rev 8 315/324 24 important notes 24.1 all devices 24.1.1 reset pin protection with lvd enabled as mentioned in note 2 below figure 135 , when the lvd is enabled, it is recommended not to connect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to filter noise on the reset line. 24.1.2 clearing active interrupts outside interrupt routine when an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the cc register may be corrupted. concurrent interrupt context the symptom does not occur when the interrupts are handled normally, that is, when: the interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine the interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine the interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following sequence: perform sim and rim operation before and after resetting an active interrupt request example 1 : sim reset flag or interrupt mask rim nested interrupt context the symptom does not occur when the interrupts are handled normally, that is, when: the interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine the interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine with higher or identical priority level the interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled important notes st72561-auto 316/324 doc id 12370 rev 8 if these conditions are not met, the symptom can be avoided by implementing the following sequence: push cc sim reset flag or interrupt mask pop cc 24.1.3 external interrupt missed to avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either ddr and or. any input signal edge during this period will not be detect ed and will not generate an interrupt. this case can typically occur if the application refreshes the port configuration registers at intervals during runtime. workaround the workaround is based on software checking the level on the interrupt pin before and after writing to the pxor or pxddr registers. if there is a level change (depending on the sensitivity programmed for this pin) the interr upt routine is invoked us ing the call instruction with three extra push instructions before executing the interrupt routine (this is to make the call compatible with the iret instruction at the end of the interrupt service routine). but detection of the level change does ensure that edge occurs during the critical 1 cycle duration and the interrupt has been missed. this may lead to occurrence of same interrupt twice (one hardware and another with software call). to avoid this, a semaphore is set to '1' before checking the level change. the semaphore is changed to level '0' inside the interrupt routine. when a level change is detected, the semaphore status is checked and if it is '1' this means that the last interrupt has been missed. in this case, the interrupt rout ine is invoked with the call instruction. there is another possible case, that is, if writing to pxor or pxddr is done with global interrupts disabled (interrupt mask bit set). in this case, the semaphore is changed to '1' when the level change is detected. detecting a missed interrupt is done after the global interrupts are enabled (interrupt mask bit reset) and by checking the status of the semaphore. if it is '1' this means that the last interrupt was missed and the interrupt routine is invoked with the call instruction. to implement the workaround, the following software sequence is to be followed for writing into the pxor/pxddr registers. the example is for port pf1 with falling edge interrupt sensitivity. the software sequence is given for both cases (global interrupt disabled/enabled). case 1: writing to pxor or pxddr with global interrupts enabled: ld a,#01 ld sema, a; set the semaphore to '1' ld a, pfdr and a, #02 ld x, a; store the level before writing to pxor/pxddr ld a, #$90 ld pfddr, a; write to pfddr ld a,#$ff ld pfor, a ; write to pfor st72561-auto important notes doc id 12370 rev 8 317/324 ld a, pfdr and a, #02 ld y, a; store the level after writing to pxor/pxddr ld a, x; check for falling edge cp a, #02 jrne out tnz y jrne out ld a, sema; check the semaphore status if edge is detected cp a, #01 jrne out call call_routine; call the interrupt routine out:ld a,#00 ld sema, a .call_routine; entry to call_routine push a push x push cc .ext1_rt; entry to interrupt routine ld a, #00 ld sema, a iret case 2: writing to pxor or pxddr with global interrupts disabled: sim; set the interrupt mask ld a, pfdr and a, #$02 ld x, a; store the level before writing to pxor/pxddr ld a, #$90 ld pfddr, a; write into pfddr ld a, #$ff ld pfor, a; write to pfor ld a, pfdr and a, #$02 ld y, a; store the level after writing to pxor/pxddr ld a, x; check for falling edge cp a, #$02 jrne out tnz y jrne out ld a, #$01 ld sema, a; set the semaphore to '1' if edge is detected rim; reset the interrupt mask ld a, sema; check the semaphore status cp a, #$01 jrne out call call_routine; call the interrupt routine rim out:rim jp while_loop .call_routine; entry to call_routine push a push x important notes st72561-auto 318/324 doc id 12370 rev 8 push cc .ext1_rt; entry to interrupt routine ld a, #$00 ld sema, a iret 24.1.4 unexpected reset fetch if an interrupt request occurs while a "pop cc" instruction is executed, the interrupt controller does not reco gnize the source of th e interrupt and, by def ault, passes the reset vector address to the cpu. workaround to solve this issue, a "pop cc" instruction mu st always be preceded by a "sim" instruction. 24.1.5 header time-out does not prevent wake-up from mute mode normally, when linsci is configured in lin slave mode, if a header time-out occurs during a lin header reception (that is, header length > 57 bits), the lin header error bit (lhe) is set, an interrupt occurs to inform the application but the linsci should stay in mute mode, waiting for the next header reception. problem description the linsci sampling period is tbit / 16. if a lin header time-out occurs between the 9th and the 15th sample of the identifier field stop bit (refer to figure 155 ), the linsci wakes up from mute mode. nevertheless, lhe is se t and lin header dete ction flag (lhdf) is kept cleared. in addition, if lhe is reset by software before this 15th sample (by accessing the scisr register and reading the scidr register in the li nsci interrupt routine), the linsci will generate another linsci interrupt (due to the rdrf flag setting). impact on application software may execute the interrupt routine twice after header reception. moreover, in recept ion mode, as the receiver is no lon ger in mute mode, an interrupt will be generated on each data byte reception. workaround the problem can be detected in the linsci interrupt routine. in case of timeout error (lhe is set and lhlr is loaded with 00h), the software can check the rwu bit in the scicr2 register. if rwu is cleared, it can be set by software. refer to figure 156 . workaround is shown in bold characters. st72561-auto important notes doc id 12370 rev 8 319/324 figure 155. header reception event sequence figure 156. linsci interrupt routine 24.1.6 can fifo corruption the becan fifo gets corrupted when a message is received and simultaneously a message is released while fmp = 2. for details and a description of the workaround refer to fifo corruption . lin synch lin synch identifier field field break t header active mode is set rdrf flag is set critical window id field stop bit (rwu is cleared) @interrupt void linsci_it ( void ) /* linsci interrupt routine */ { /* clear flags */ scisr_buffer = scisr; scidr_buffer = scidr; if ( scisr_buffer & lhe )/* header error ? */ { if (!lhlr)/* header time-out? */ { if ( !(scicr2 & rwu) )/* active mode ? */ { _asm("sim");/* disable interrupts */ scisr; scidr;/* clear rdrf flag */ scicr2 |= rwu;/* set mute mode */ scisr; scidr;/* clear rdrf flag */ scicr2 |= rwu;/* set mute mode */ _asm("rim");/* enable interrupts */ } } } } example using cosmic compiler syntax important notes st72561-auto 320/324 doc id 12370 rev 8 24.2 flash/fastrom devices only 24.2.1 linsci wrong break duration sci mode a single break characte r is sent by setting and resetting the sbk bit in the scicr2 register. in some cases, the break character may have a longer duration than expected: 20 bits instead of 10 bits if m = 0 22 bits instead of 11 bits if m = 1 in the same way, as long as the sbk bit is se t, break characters are sent to the tdo pin. this may lead to generate one break more than expected. occurrence the occurrence of the problem is random and proportional to the baud rate. with a transmit frequency of 19200 baud (f cpu = 8 mhz and scibrr = 0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with th e communication protocol in the application, software can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. this can be ensured by temporarily disabling interrupts. the exact sequence is: disable interrupts reset and set te (idle request) set and reset sbk (break request) re-enable interrupts lin mode if the line bit in the scicr3 is set and the m bi t in the scicr1 register is reset, the linsci is in lin master mode. a single break character is sent by setting and resetting the sbk bit in the scicr2 register. in some cases, the break character may have a longer duration than expected: 24 bits instead of 13 bits occurrence the occurrence of the problem is random and proportional to the baud rate. with a transmit frequency of 19200 baud (f cpu = 8 mhz and scibrr = 0xc9), the wrong break duration occurrence is around 1%. st72561-auto important notes doc id 12370 rev 8 321/324 analysis the lin protocol specifies a minimum of 13 bits for the break duration, but there is no maximum value. nevertheless, the maximum length of the header is specified as (14 + 10 + 10 + 1) x 1.4 = 49 bits. this is composed of: the synch break field (14 bits) the synch field (10 bits) the identifier field (10 bits) every lin frame starts with a break character. adding an idle character increases the length of each header by 10 bits. when the problem occurs, the header length is increased by 11 bits and becomes ((14 + 11) + 10 + 10 + 1) = 45 bits. to conclude, the problem is not always critical for lin communication if the software keeps the time between the sync field and the id smaller than 4 bits, that is, 208s at 19200 baud. the workaround is the same as for sci mode but considering the low probability of occurrence (1%), it may be better to keep the break generation sequence as it is. 24.2.2 16-bit and 8- bit timer pwm mode in pwm mode, the first pwm pulse is missed a fter writing the value fffch in the oc1r or oc2r register. 24.3 rom devices only 24.3.1 16-bit timer pwm mode buffering feature change in all devices, the frequency and period of the pwm signal are controlled by comparing the counter with a 16-bit buffer updated by the ocihr and ocilr registers. in rom devices, contrary to the description in pulse width modulation mode , the output compare function is not inhibited after a write instru ction to the ocihr register. in stead the buffer update at the end of the pwm period is inhibited until ocilr is written. this improved buffer handling is fully compatible with applications written for flash devices. revision history st72561-auto 322/324 doc id 12370 rev 8 25 revision history table 129. document revision history date revision changes 03-may-2004 1 added tqfp 10x10 package removed internal rc updated figure 11: clock, reset and supply block diagram added note on monotonous v dd ramp on section 5.6.1: low voltage detector (lvd) added caution art ext clock not available in halt see section 11: pwm auto- reload timer (art) added note ?once the ocie bit is set both output compare features may trigger...? and ?once the icie bit is set both input capture features may trigger...? in 8-bit timer section 13: 8-bit timer (tim8) . changed clock from fcpu/8000 to fosc2/8000 in section 13: 8-bit timer (tim8) changed description of csr register to read only except bit 2 r/w section 13: 8-bit timer (tim8) added note to spi slave freq. and updated master mode procedure in section 14: serial peripheral interface (spi) changed description of nf bit in section 15.10: lin mode register description removed ?configurable timer resolution? under "time triggered communication option" from section 17: becan controller (becan) added clearing interrupts limitation and sci wrong break duration to chapter 24: important notes removed becan time triggered mode feature from section 17: becan controller (becan) renamed cmsr rx and tx bits to rec and tran in section 17: becan controller (becan) added becan fifo corruption limitation fifo corruption modified i inj for port b3 in section 20.9.1: gene ral characteristics 11-may-2004 2 modified clearing interrupts limitation in chapter 24: important notes 12-may-2005 3 lin sci tm changed to linsci tm throughout document. changed name of wwdgr register to wdgwr in table 4: hardware register map changed static power consumption to 200 ua typ in section 20.9.1: general characteristics modified readout protection description in section 3.3.1: read-out protection added section 24.1: all devices modified figure 135: reset pin protec tion when lvd is enabled and figure 136: reset pin protection when lvd is disabled and related notes added 48k rom version in table 2: product overview , figure 5: memory map and figure 154: st72561xxx-auto rom commercial product structure 24-oct-2005 4 added standard version 16k rom/flash devices modified data retention in section 20.7: memory characteristics added ?6? and ?3? standard version device type coding to figure 152: st72f561xxx- auto flash commercial product structure and figure 154: st72561xxx-auto rom commercial product structure modified power consumption section 20.4: supply current characteristics added cdm in electrostatic discharge (esd) added ?external interrupt missed? section 24.1.3: external interrupt missed st72561-auto revision history doc id 12370 rev 8 323/324 23-jun-2006 5 replaced tqfp with lqfp packages throughout document changed device summary on table 2: product overview changed section 8.2.1: input modes changed title of section 8.4: i/o port register configurations from ?i/o port implementation? to ?i/o port register configurations? changed master mode operation corrected name of bit 5 in spicsr register in table 59: spi register map and reset values changed section 20.5.2: pll characteristics added links to table 111: absolute maximum ratings and table 112: electrical sensitivities in section 20.8.3: absolute maximum ratings (electrical sensitivity) removed emc protection circuitry in figure 136: reset pin pr otection when lvd is disabled (device works correctly without these components) changed section 20.12.1: spi - serial peripheral interface changed title of figure 147: 64-pin low profile quad flat package (14x14) changed title of figure 148: 32-pin low profile quad flat package (7x7) changed title of figure 149: 44-pin low profile quad flat package (10x10) changed notes in table 21.3: thermal characteristics changed afi mapping for option byte 1 changed figure 154: st72561xxx- auto rom commercial product structure , figure 153: st72p56 1xxx-auto fastrom commercial product structure and figure 152: st 72f561xxx-auto flash commerc ial product structure changed section 20.12.1: spi - serial peripheral interface deleted section 15.1.5 ?clearing active inte rrupts outside interrupt routine? (text already exists in section 24.1.2: clearing active interrupts outside interrupt routine ) added section 24.1.5: header time-out does not prevent wake-up from mute mode 11-mar-2008 6 removed ?f? from root part numbers and removed references to ?automotive only? devices in the table 2: product overview removed ?mcu? from the url reference in st72561-auto microcontroller option list and chapter 23: development tools removed section on ?soldering a nd glueability information? and replaced with section 21.4: packaging for automatic handling removed references to standard device temperature codes from figure 154: st72561xxx-auto rom commercial product structure , figure 153: st72p561xxx- auto fastrom commercial product structure and figure 152: st72f561xxx-auto flash commercial product structure made small editing changes throughout document to improve readability 02-aug-2010 7 updated following figures: ? figure 152: st72f561xxx-auto flas h commercial product structure ? figure 153: st72p561xxx-auto fastro m commercial product structure ? figure 154: st72561xxx-auto rom commercial product structure added chapter 21.4: packaging for automatic handling 03-jan-2011 8 reinstated : chapter 17: becan controller (becan) table 129. document revision history (continued) date revision changes st72561-auto 324/324 doc id 12370 rev 8 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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